Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits

Abstract

This chapter discusses about the behavior of Carbon Nanotube (CNT) different structures which can be used as interconnect in Very Large Scale (VLSI) circuits in nanoscale regime. Also interconnect challenges in VLSI circuits which lead to use CNT as interconnect instead of Cu, is reviewed. CNTs are classified into three main types including Single-walled Carbon Nanotube (SWCNT), CNT Bundle, and Multi-walled Carbon Nanotube (MWCNT). Because of extremely high quantum resistance of a SWCNT which is about 6.45 kΩ, rope or bundle of CNTs are used which consist of parallel CNTs in order to overcome the high delay time due to the high intrinsic (quantum) resistance. Also MWCNTs which consist of parallel shells, present much less delay time with respect to SWCNTs, for the application as interconnects. In this chapter, first a short discussion about interconnect challenges in VLSI circuits is presented. Then the repeater insertion technique for the delay reduction in the global interconnects will be studied. After that, the parameters and circuit model of a CNT will be discussed. Then a brief review about the different structures of CNT interconnects including CNT bundle and MWCNT will be presented. At the continuation, the time domain behavior of a CNT bundle interconnect in a driver-CNT bundle-load configuration will be discussed and analyzed. In this analysis, CNT bundle is modeled as a transmission line circuit model. At the end, a brief study of stability analysis in CNT interconnects will be presented. Interconnect Challenges in VLSI CircuitsAs interconnect feature sizes shrink, copper resistivity increases due to surface and grain boundary scatterings and also surface roughness [1]. Furthermore, wires, especially power and ground lines, are becoming more and more vulnerable to electromigration because of rapid increases in current densities [2]. The resistance of copper interconnects, with crosssectional dimensions of the order of the mean free path of electrons (~40 nm in Cu at room temperature) in current and imminent technologies [2], is increasing rapidly under the combined effects of enhanced grain boundary scattering, surface scattering and the presence of the highly resistive diffusion barrier layer [3]. The steep rise in parasitic resistance of copper interconnects poses serious challenges for interconnect delay [2]

Scanning Probe Techniques for Characterization of Vertically Aligned Carbon Nanotubes

“…Investigation of the VA CNT array by the STM method: (a) 3D STM image of the VA CNT array; and (b) CVCs of an individual nanotube (solid line) and substrate (dashed line)[23].Scanning Probe Techniques for Characterization of Vertically Aligned Carbon Nanotubes http://dx.doi.org/10.5772/intechopen.78061CNT, the resistivity of VA CNT was (8.32 ± 3.18)•10 −4 Ωm. The obtained value of the resistivity of multi-walled VA CNT correlates well with the literature data[41].…”

Power Withstanding Capability and Transient Temperature of Carbon Nanotube-Based Nano Electrical Interconnects

“…In future, CNTs would be used as an attractive material for VLSI device components. CNT and graphene-based hybrid materials and composite materials would be given more priority in optoelectronic devices, electrical contacts, interconnects, sensors, and circuits [44][45][46][47]. Even though CNTs shows promising results for electrical interconnect applications, full implementation of these CNT electrical interconnects in electronic circuits, and Integrated circuits (IC) would take another few years.…”