Peak Power Reduction Through Dynamic Partitioning of Scan Chains

Almukhaizim, Sobeeh; Sinanoglu, Ozgur

doi:10.1109/test.2008.4700573

Cited by 26 publications

(15 citation statements)

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“…Over the years, numerous techniques for test power reduction in shift and capture modes have been proposed, including test scheduling [9], test vector reordering [10], partitioning [11], X-fills [12][13][14], blocking gate [15][16][17][18][19], and clock gating [20][21][22][23], etc. In general, an ideal test power reduction strategy should include the following properties:…”

Section: Open Accessmentioning

confidence: 99%

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Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Lin

2011

JLPEA

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Section: Open Accessmentioning

confidence: 99%

“…Each group is either shifted at a different time within a clock cycle [32] or shifted at the different clock cycles [11]. Figure 6a shows the clock scheme to shift three scan chains at the different times, t 1 , t 2 and t 3 , in a shift cycle [32].…”

Section: Clock Application Schemesmentioning

confidence: 99%

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Lin

2011

JLPEA

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“…In both cases, peak power violations occur due to concurrent switching activities much higher than that seen during functional operation. Peak power is the maximum power consumed during an observation period or otherwise is the maximum rate of change of energy flow at every instant within the observation period [4,10], P (peak) = max (E/∆t). While low power fills and flop Q gating help in limiting the switching during load/unload cycles, they are not of much use in limiting the switching during capture cycles.…”

Section: Introductionmentioning

confidence: 99%

“…There are lots of other methods also being used for the overall reduction in average power and peak power during shift/capture phases [1][2][3][4][10][11][12][13][14][15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

Slack-based approach for peak power reduction during transition fault testing

Baby¹,

Sarathi²

2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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Peak power consumption during test for the low power devices is a major concern [2, 3, 4]. Excessive peak power may result in test failures of functionally good devices. Huge peaks in the instantaneous power consumption will result in high rates of change of current (di/dt) causing adverse noise effects like VDD-drop and ground-bounce [1,2,3,4]. Also, a high frequency of occurrence of high di/dt may cause severe decrease in the reliability of the circuit [1]. Hence the process of testing low power devices must be peak power aware.This paper provides a method to minimize the peak power during speed capture phase by partitioning the nodes into two zones based on their timing slacks. One of the zones contains the timing-critical nodes, while the other contains the non timing-critical ones. Each zone may be split into multiple bins. Test patterns are generated independently for each bin, targeting the nodes belonging to that bin alone, thus reducing the size of the target set. It is very important that the peak power consumed by the test patterns for each bin in the timing-critical zone is well within the tolerable limit. The bins in the non timing-critical zone may be allowed to have peak power consumptions very close to the limit or even marginally higher because the large positive slacks on these nodes will make up for the extra delay through the cells caused by VDD-drop/ground-bounce. This approach allows the designer to have a better control over each pattern and also helps to minimize the effects of high peak power and high di/dt. KeywordsDFT, ATPG, power-aware test, capture cycle, at-speed test and power budget.

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“…Various techniques have been proposed in the literature to address this issue, which can be categorized into: (i). DfT-based techniques that change the circuit under test (CUT) for test power reduction (e.g., [2,25,36,39]); (ii). low-power test scheduling algorithms that apply modular tests at different time according to given power constraints (e.g., [7,12,26]); (iii).…”

Section: Introductionmentioning

confidence: 99%