On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment

Liu, Xiao; Xu, Qiang

doi:10.1109/test.2009.5355554

Cited by 27 publications

(7 citation statements)

References 34 publications

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“…Table II presents the shift power obtained with our approach. We also compare our result with other X-filling techniques like Adjacent-fill [8], CSC-fill [17], i-fill [9], and S-filling [18]. It is evident from the Table II that, the shift power is comparable with the Adjacent-fill which is known to be the efficient method to reduce the shift power.…”

Section: Resultsmentioning

confidence: 73%

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

Sivanantham

Sarathkumar

Manuel

et al. 2012

2012 International Symposium on Electronic System Design (ISED)

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In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1's or 0's using the proposed don't care filling technique, namely CSP − f illing in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS'89 benchmark circuits show that, the CSP − f illing technique provides a significant reduction in both shift and capture transitions in test mode.

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Section: Resultsmentioning

confidence: 73%

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

Sivanantham

Sarathkumar

Manuel

et al. 2012

2012 International Symposium on Electronic System Design (ISED)

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“…In order to further illustrate the power reduction capability of the proposed technique, we provide herein a comparison to the two most effective scan power reduction schemes [24] that are based on sequential linear compression schemes, as summarized in Table V. The proposed scheme in general delivers higher percentage of peak and average power reductions.…”

Section: Resultsmentioning

confidence: 99%

“…Linear constraint propagation is performed during the X-filling process to guarantee the compressibility of the filled test cubes. The technique proposed in [24] improves the aforementioned X-filling technique by filling the X values according to the power impact of the free bits in the seeds and performing a post-processing adjustment of the filled test cube. A low power compression technique based on scan chain partitioning is proposed in [30].…”

Section: Related Workmentioning

confidence: 99%

“…It has been widely reported that uncontrolled scan power dissipation significantly degrades the scan test quality by incurring chip damage and overscreeninginduced yield loss [1]. While reducing power for non-compressed test vectors constitutes a formidable research challenge as exemplified by the number of research works published in the area [14]- [19], [29], the possibly conflicting compression goal elevates the challenge of power reduction to a highly challenging plane, as shown by the limited number of works on this topic [6], [24], [30]. The attainment of either target necessitates the appropriate utilization of the unspecified bits (don't cares) in the test cubes.…”

Section: Introductionmentioning

confidence: 99%

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Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection

Chen

Orailoğlu

2012

IEEE Trans. VLSI Syst.

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XOR network-based on-chip test compression schemes have been widely employed in large industrial scan designs due to their high compression ratio and efficient decompression mechanism. Nevertheless, such a scheme necessitates high unspecified bit ratios in the original test cubes, resulting in quite significant difficulties in preprocessing test cubes for scan power reduction. The linear mapping from the original cubes to the compressed seeds typically provides extra degrees of flexibility as multiple seeds may reconstruct the test cube. Due to the highly divergent power impact of distinct seeds though, appreciable power reductions in the decompressed test data can be attained through the pinpointing of the power-optimal seeds during the compression phase. This work explores the aforementioned flexibility in the seed space, and outlines a mathematical and algorithmic framework for a poweraware linear test compression scheme. The proposed technique incurs no hardware overhead over the traditional linear compression scheme; it can be easily embedded furthermore into the industrial test compaction/compression flow. Experimental results confirm that the proposed technique delivers significant scan power reduction with negligible impact on the compression ratio.

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“…An encoding scheme should therefore allow feeding scan chains with patterns having reduced the amount of toggling. In response to these challenges, several low power test data encoding schemes were presented [3], [28], [30], [32], [33], [38], [55]. Some of them rest on conventional LFSR reseeding techniques with certain extensions reducing the scan-in transition probability.…”

Section: A Prior Workmentioning

confidence: 99%

Isometric Test Data Compression

Kumar

Kassab

Moghaddam

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The paper introduces a novel test data compression scheme, which is primarily devised for low power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide ATPG to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.Index Terms-Design for testability, embedded deterministic test, low power test, scan-based designs, test compression.

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On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment

Abstract: Abstract

Cited by 27 publications

References 34 publications

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection

Isometric Test Data Compression

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