Slack-based approach for peak power reduction during transition fault testing

Abstract

Peak power consumption during test for the low power devices is a major concern [2, 3, 4]. Excessive peak power may result in test failures of functionally good devices. Huge peaks in the instantaneous power consumption will result in high rates of change of current (di/dt) causing adverse noise effects like VDD-drop and ground-bounce [1,2,3,4]. Also, a high frequency of occurrence of high di/dt may cause severe decrease in the reliability of the circuit [1]. Hence the process of testing low power devices must be peak power aware.This paper provides a method to minimize the peak power during speed capture phase by partitioning the nodes into two zones based on their timing slacks. One of the zones contains the timing-critical nodes, while the other contains the non timing-critical ones. Each zone may be split into multiple bins. Test patterns are generated independently for each bin, targeting the nodes belonging to that bin alone, thus reducing the size of the target set. It is very important that the peak power consumed by the test patterns for each bin in the timing-critical zone is well within the tolerable limit. The bins in the non timing-critical zone may be allowed to have peak power consumptions very close to the limit or even marginally higher because the large positive slacks on these nodes will make up for the extra delay through the cells caused by VDD-drop/ground-bounce. This approach allows the designer to have a better control over each pattern and also helps to minimize the effects of high peak power and high di/dt. KeywordsDFT, ATPG, power-aware test, capture cycle, at-speed test and power budget.