At-speed capture global noise reduction &amp; low-power memory test architecture

Bhaskaran, Bonita; Chadalavada, Sailendra; Sarangi, Shantanu; Valentine, Nithin; Nerallapally, Venkat Abilash Reddy; Abdollahian, Ayub

doi:10.1109/vts.2017.7928936

Cited by 3 publications

(3 citation statements)

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“…Bhaskaran et al [17] presented a design-for-test (DFT) architecture that reduces dynamic power during memory testing. Memory tests incur a lot of toggling and may lead to voltage droop and peak current limits crossing.…”

Section: Test Schedulingmentioning

confidence: 99%

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Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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Newer defects in memories arising from shrinking manufacturing technologies demand improved memory testing methodologies. The percentage of memories on chips continues to rise. With shrinking technologies (10 nm up to 1.8 nm), the structure of memories is becoming denser. Due to the dense structure and significant portion of a chip, the nanometer memories are highly susceptible to defects. High-frequency specifications, the complexity of internal connections, and the process variation due to newer manufacturing technology further increased the probability of the physical failure of memories to a great extent. Memories need to be defect-free for the chip to operate successfully. Therefore, testing embedded memories has become crucial and is taking significant test costs. Researchers have proposed multiple approaches considering these factors to test the nanometer memories. They include using new fault models, march algorithms, memory built-in self-test (MBIST) architectures, and validation strategies. This paper surveys the methodologies presented in recent times. It discusses the core principles used in them, along with benefits. Finally, it discusses key opens in each and offers the scope for future research.

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Section: Test Schedulingmentioning

confidence: 99%

“…Here, the author creates a control chain with bits for each MBIST controller. The output of this chain controls the mbist_en port instead of the clock-gating cell as in [17]. The mbist_en port also drives logic to enable the clock to memory and MBIST controller.…”

Section: Test Schedulingmentioning

confidence: 99%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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“…In the context of this paper, previous work can be divided into the following categories: Analyzing aging and IR-drop effects: While investigating how aging or IR-drop alone (e.g., [12], [13]) can increase the delay of circuits has been largely explored in the past years, research w.r.t estimating the required timing guardbands due to both of them jointly is still in its infancy. In [5], authors assumed that the rate of ∆V th change due to BTI is significantly larger than the rate of V dd change caused by IR-drops and as a result it was concluded that aging and IR-drop effects can be independently considered.…”

Section: Related Workmentioning

confidence: 99%

Modeling the Interdependences Between Voltage Fluctuation and BTI Aging

Salamin

Santen

Amrouch

et al. 2019

IEEE Trans. VLSI Syst.

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With technology scaling the susceptibility of circuits to different reliability degradations is steadily increasing. Aging in transistors due to Bias Temperature Instability (BTI) and voltage fluctuation in the power delivery network of circuits due to IR-drops are the most prominent. In this work, we are reporting for the first time, that there are interdependencies between voltage fluctuation and BTI aging, that are non-negligible. Modeling and investigating the joint impact of voltage fluctuation and BTI aging on the delay of circuits, while remaining compatible with the existing standard design flow, is indispensable in order to answer the vital question, "What is an efficient (i.e. small, yet sufficient) timing guardband to sustain the reliability of circuit for the projected lifetime?" This is, concisely, the key goal of this paper. Achieving that would not be possible without employing a physics-based BTI model that precisely describes the underlying generation and recovery mechanisms of defects under arbitrary stress waveforms. For this purpose, our model is validated against varied semiconductor measurements covering a wide range of voltage, temperature, frequency and duty cycle conditions.To bring reliability awareness to existing EDA tool flows, we create standard cell libraries that contain the delay information of cells under the joint impact of aging and IR-drop. Our libraries can be directly deployed within the standard design flow because they are compatible with existing commercial tools (e.g., Synopsys and Cadence). Hence, designers can leverage the mature algorithms of these tools to accurately estimate the required timing guardbands for any circuit despite its complexity. Our investigation demonstrates that considering aging and IRdrop effects independently, as done in state of the art, leads to employing insufficient and thus unreliable guardbands because of the non-negligible (on average 15% and up to 25%) underestimations. Importantly, considering interdependencies between aging and IR-drop does not only allow correct guardband estimations but it also results in employing more efficient guardbands.

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