Negative Capacitance Field-Effect Transistor (NCFET) is an emerging technology that incorporates a ferroelectric layer within the transistor gate stack to overcome the fundamental limit of sub-threshold swing in transistors. Even though physics-based NCFET models have been recently proposed, system-level NCFET models do not exist and research is still in its infancy. In this work, we are the first to investigate the impact of NCFET on performance, energy and cooling costs in many-core processors. Our proposed methodology starts from physics, where the effects of ferroelectricity do occur, all the way up to the system level, where the performance and power of a many-core is ultimately affected. Our methodology allows for the first time the exploration of the new trade-offs between performance gains and power losses that NCFET brings to system-level designers. It demonstrates that an optimal ferroelectric thickness does exist. In addition, it reveals that current power management techniques fail when NCFET (with a thick ferroelectric layer) comes into play.
Negative Capacitance Field-Effect Transistor (NCFET) pushes the sub-threshold swing beyond its fundamental limit of 60 mV/decade by incorporating a ferroelectric material within the gate stack of transistor. Such a material manifests itself as a negative capacitance (NC) that provides an internal voltage amplification for the transistor resulting in higher ON current levels. Hence, the performance of processors can be boosted while the operating voltage still remains the same. However, having a negative capacitance makes the total gate terminal capacitance larger. While, the impact of that on compensating the gained performance has already been studied in literature, this work is the first to explore the impact of negative capacitance on exacerbating the IR-drop problem in processors. In fact, voltage fluctuation in the Power Delivery Network (PDN) due to IR-drops is one of the prominent sources of performance loss in processors, which necessitates adding timing guardbands to sustain a reliable operation during runtime. In this work, we study NC-FinFET standard cells and processor for the 7 nm technology node. We demonstrate that NC, on the one hand, results in larger IR-drops due to the increase in current densities across the chip, which leads to a higher stress on the PDN. However, the internal voltage amplification provided by NC, on the other hand, compensates to some degree the voltage reduction caused by IR-drop. We investigate, from physics all the way to full-chip (GDSII) level, how the overall performance of a processor is affected under the impact that NC has on magnifying and compensating IR-drop.
Negative Capacitance Field-Effect Transistor (NCFET) has recently attracted significant attention. In the NCFET technology with a thick ferroelectric layer, voltage reduction increases the leakage power, rather than decreases, due to the negative Drain-Induced Barrier Lowering (DIBL) effect. This work is the first to demonstrate the far-reaching consequences of such an inverse dependency w.r.t. the existing power management techniques. Moreover, this work is the first to demonstrate that state-of-the-art Dynamic Voltage Scaling (DVS) techniques are sub-optimal for NCFET. Our investigation revealed that the optimal voltage at which the total power is minimized is not necessarily at the point of the minimum voltage required to fulfill the performance constraint (as in traditional DVS). Hence, an NCFET-aware DVS is key for high energy efficiency. In this work, we therefore propose the first NCFET-aware DVS technique that selects the optimal voltage to minimize the power following the dynamics of workloads. Our experimental results of a multi-core system demonstrate that NCFET-aware DVS results in 20% on average, and up to 27% energy saving while still fulfilling the same performance constraint (i.e., no trade-offs) compared to traditional NCFET-unaware DVS techniques.
With technology scaling the susceptibility of circuits to different reliability degradations is steadily increasing. Aging in transistors due to Bias Temperature Instability (BTI) and voltage fluctuation in the power delivery network of circuits due to IR-drops are the most prominent. In this work, we are reporting for the first time, that there are interdependencies between voltage fluctuation and BTI aging, that are non-negligible. Modeling and investigating the joint impact of voltage fluctuation and BTI aging on the delay of circuits, while remaining compatible with the existing standard design flow, is indispensable in order to answer the vital question, "What is an efficient (i.e. small, yet sufficient) timing guardband to sustain the reliability of circuit for the projected lifetime?" This is, concisely, the key goal of this paper. Achieving that would not be possible without employing a physics-based BTI model that precisely describes the underlying generation and recovery mechanisms of defects under arbitrary stress waveforms. For this purpose, our model is validated against varied semiconductor measurements covering a wide range of voltage, temperature, frequency and duty cycle conditions.To bring reliability awareness to existing EDA tool flows, we create standard cell libraries that contain the delay information of cells under the joint impact of aging and IR-drop. Our libraries can be directly deployed within the standard design flow because they are compatible with existing commercial tools (e.g., Synopsys and Cadence). Hence, designers can leverage the mature algorithms of these tools to accurately estimate the required timing guardbands for any circuit despite its complexity. Our investigation demonstrates that considering aging and IRdrop effects independently, as done in state of the art, leads to employing insufficient and thus unreliable guardbands because of the non-negligible (on average 15% and up to 25%) underestimations. Importantly, considering interdependencies between aging and IR-drop does not only allow correct guardband estimations but it also results in employing more efficient guardbands.
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