Test power minimization of VLSI circuits: A survey

Kumar, Ganesan Senthil; Paramasivam, K.

doi:10.1109/icccnt.2013.6726569

Cited by 4 publications

(2 citation statements)

References 34 publications

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“…It also describes basic x-filling techniques like 0-fill, 1-fill, and MT-fill. Another survey for test power minimization is presented in [8]. Along with shift power reduction techniques for regular-scan, it summarizes power reduction when scan compression methodologies are being used.…”

Section: Previous Surveys On Low Power Testmentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

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Section: Previous Surveys On Low Power Testmentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

View full text Add to dashboard Cite

show abstract

“…Another survey for test power minimization is presented in [10]. Along with shift power reduction techniques for regular-scan, it summarizes power reduction when scan compression methodologies are being used.…”

Section: Previous Surveys On Low Power Testmentioning

confidence: 99%

A survey of scan-capture power reduction techniques

Sontakke,

Dickhoff

2023

IJECE

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With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

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Energy efficient low‐power full‐adder by 65 nm CMOS technology in ALU

N¹,

Paramasivam²

2018

Concurrency and Computation

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The arrangement of energy efficient low-power full adder has vital role in VLSI systems. In this paper Energy Efficient Low-power 9T full-adder is proposed. Its functioning basis of Power Delay Product (PDP), Delay, power and area is distinguished in accordance with that current 1 bit full-adder simulated by utilizing various Complementary MOS logic designs. Output provides an average minimization of 99.28% in power usage, 67.87% in area, 99.89% in delay, and 99.99% in Power-Delay Product (PDP) distinguished to the traditional 28 Transistors CMOS logic. The ALU design has been implemented using 9T full adder. These logic gates are analysis at 65 nm technology of CMOS by utilizing Schematic Editor Tool. KEYWORDS area, average power, delay, power delay product (PDP)The 22T Zhuang Full-Adder 6 which minimizes transistor count and the inverter additional which is utilized to create inverter of Xnor (Xor). As contradictory to 22T adder and TG adder enforces gate xor instead of multiplexer for making S out . 22T Full-Adder is as depicted in Figure 2.Concurrency Computat Pract Exper. 2019;31:e4741.wileyonlinelibrary.com/journal/cpe

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Test power minimization of VLSI circuits: A survey

Cited by 4 publications

References 34 publications

Developments in scan shift power reduction: a survey

Developments in scan shift power reduction: a survey

A survey of scan-capture power reduction techniques

Energy efficient low‐power full‐adder by 65 nm CMOS technology in ALU

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