Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Lin, Xijiang

doi:10.3390/jlpea1030357

Cited by 4 publications

(4 citation statements)

References 34 publications

(47 reference statements)

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“…(I) The approach of changing test data mostly tries to reduce SSA by filling X-bits to reduce scan flip-flop toggle count (FFTC), or by considering SSA or FFTC reduction during test pattern generation. Similarly, test data can also be manipulated with additional DFT hardware [3]. In addition, a novel X-filling method was proposed by considering scan reordering to reduce shift power [21].…”

Section: Reduction Of Ir-drop In Scan Shiftingmentioning

confidence: 99%

“…Power reduction is growing even more complicated as artificial intelligence (AI) is increasingly used in IoT and mobile devices [1]. Usually, power consumption during function mode can be significantly reduced through a comprehensive design of various power management structures [2], [3].…”

Section: Introductionmentioning

confidence: 99%

“…This increases switching activity during scan test, resulting in excessive test power compared with function power. The gap between function power and test power keeps widening since more innovative power management structures are developed to enable low-power ICs [3], [5].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting

SHI,

HOLST,

WEN

2023

IEICE Trans. Inf. & Syst.

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High power dissipation during scan test often causes undue yield loss, especially for low-power circuits. One major reason is that the resulting IR-drop in shift mode may corrupt test data. A common approach to solving this problem is partial-shift, in which multiple scan chains are formed and only one group of scan chains is shifted at a time. However, existing partial-shift based methods suffer from two major problems:(1) their IR-drop estimation is not accurate enough or computationally too expensive to be done for each shift cycle; (2) partial-shift is hence applied to all shift cycles, resulting in long test time. This paper addresses these two problems with a novel IR-drop-aware scan shift method, featuring: (1) Cycle-based IR-Drop Estimation (CIDE) supported by a GPU-accelerated dynamic power simulator to quickly find potential shift cycles with excessive peak IR-drop; (2) a scan shift scheduling method that generates a scan chain grouping targeted for each considered shift cycle to reduce the impact on test time. Experiments on ITC'99 benchmark circuits show that: (1) the CIDE is computationally feasible; (2) the proposed scan shift schedule can achieve a global peak IR-drop reduction of up to 47%. Its scheduling efficiency is 58.4% higher than that of an existing typical method on average, which means our method has less test time.

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Section: Reduction Of Ir-drop In Scan Shiftingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting

SHI,

HOLST,

WEN

2023

IEICE Trans. Inf. & Syst.

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“…Therefore the power restriction for ATPG includes that: a. "Low-Power ATPG" to avoid throw way good chips and hence lower the manufacturing yield [3]. b.…”

Section: X-aware Atpgmentioning

confidence: 99%

Scan Based Silicon Debug

Huang¹

2012

ECS Trans.

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Silicon debug is very important to make a VLSI product quickly available to the market and meet time-to-volume requirement. With designs becoming more complicated, the time spent for silicon debug is taking more fraction of the whole design cycle. Many silicon bugs are found at system level or at chip level while applying a functional test sequence. Comparing to scan test failures, debugging the functional failures is more timeconsuming. Scan-based diagnosis is more mature in the recent years and already widely used by many semiconductor companies as defect localization and yield ramp up tool. Meanwhile people have already started to adopt the scan-based diagnosis in silicon debug. Nevertheless, since the objective and application are different in manufacturing diagnosis and silicon debug, their application flows could be also different. In this paper, we will discuss the challenge and possible solutions for using scan-based diagnosis flow on silicon debug.

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