Scan Based Silicon Debug

Abstract

Silicon debug is very important to make a VLSI product quickly available to the market and meet time-to-volume requirement. With designs becoming more complicated, the time spent for silicon debug is taking more fraction of the whole design cycle. Many silicon bugs are found at system level or at chip level while applying a functional test sequence. Comparing to scan test failures, debugging the functional failures is more timeconsuming. Scan-based diagnosis is more mature in the recent years and already widely used by many semiconductor companies as defect localization and yield ramp up tool. Meanwhile people have already started to adopt the scan-based diagnosis in silicon debug. Nevertheless, since the objective and application are different in manufacturing diagnosis and silicon debug, their application flows could be also different. In this paper, we will discuss the challenge and possible solutions for using scan-based diagnosis flow on silicon debug.