Patterning with Amorphous Carbon Thin Films

Antonelli, G. A.; Reddy, Sirish K.; Subramonium, Pramod; Henri, Jon; Sims, Jim; O'Loughlin, Jennifer L.; Shamma, Nader; Schlosser, Don; Mountsier, Tom; Guo, Wuqian; Sawin, Herb

doi:10.1149/1.3572314

Cited by 12 publications

(2 citation statements)

References 19 publications

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“…246 Further, the mechanical properties and intrinsic stresses in the spacer and associated hard mask materials must be carefully considered in order to prevent pattern collapse and line wiggling issues. 118,119,[247][248][249] The spacer material and deposition process must also be compatible with the pitch division process and hard masking materials utilized to form the initial template. In cases where a high temperature deposited a-C:H film is chosen as the template material, a similarly high temperature CVD or PECVD oxide/nitride material may be suitable.…”

Section: Spacers and Hard Masks -The Disappearing Dielectricsmentioning

confidence: 99%

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Jenkins

Austin

Conley

et al. 2019

ECS J. Solid State Sci. Technol.

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High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges. We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling. We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful” requirements for the various enabling dielectric hardmask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements. We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.

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Section: Spacers and Hard Masks -The Disappearing Dielectricsmentioning

confidence: 99%

Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Jenkins

Austin

Conley

et al. 2019

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

show abstract

“…However, amorphous carbon lms fabricated through PE-CVD inevitably contain hydrogen due to the CH-based precursor, which causes degradation of the physical properties according to the hydrogen concentration, making it challenging to obtain high-aspect-ratio patterning. [10][11][12][13][14] To overcome this problem and improve the performance of the hardmask, studies have been conducted to predict a method that may have high resistance to uorine, a major etching gas, through DFT calculation. As a result of the calculation, a method of controlling the amount of hydrogen bonded to carbon or doping other substances was suggested.…”

Section: Introductionmentioning

confidence: 99%