Parasitic S/D resistance effects on hot-carrier reliability in body-tied FinFETs

Han, Jin−Woo; Lee, Choong-Ho; Park, Donggun; Choi, Yang‐Kyu

doi:10.1109/led.2006.875721

Cited by 13 publications

(2 citation statements)

References 11 publications

(9 reference statements)

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“…In another report, it was mentioned briefly that parasitic S/D resistance in body-tied FinFETs affects hotcarrier reliability. 6) However, the internal physics and the relationship of the rate with device geometry have not been reported. It also has been not reported that what the dominant factor for parasitic S/D resistance in the bulk FinFETs is.…”

Section: Introductionmentioning

confidence: 99%

Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions

Kim¹,

Kim²,

Baek³

et al. 2007

jjap

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The impact ionization behavior of bulk fin field effect transistors (FinFETs) was investigated with respect to fin body width (W fin ) and bias conditions. As fin width decreases to less than about 50 nm, the effect of parasitic source/drain series resistance becomes significant, resulting in a decrease in the impact ionization rate due to the increasing voltage drop across the resistance. We analyzed the I SUB =I D trend depending on the bias conditions (V GS ¼ V DS and V GS ¼ V DS =2) for devices with a W fin thicker than 50 nm. Through two-dimensional device simulation, we showed the voltage drop and the peak electron temperature for various W fin . It was also shown that the contact resistivity between the source/drain and the metal electrode is very important in the bulk FinFET with a very thin fin width.

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Section: Introductionmentioning

confidence: 99%

Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions

Kim¹,

Kim²,

Baek³

et al. 2007

jjap

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“…One of the solutions is to use the body-tied (BT) FinFET. 3,4) However the shortchannel characteristics are eventually to be degraded because there is no a buried oxide (BOX) under the channel region to decrease the influence of drain electric field on the device behavior. Even though the body-on-insulator or BOI FinFET 5) was proposed to alleviate the aforementioned problems, the process for BOI formation is complicated.…”

Section: Introductionmentioning

confidence: 99%

A Three-Dimensional Simulation Study of Source/Drain-Tied Double-Gate Fin Field-Effect Transistor Design for 16-nm Half-Pitch Technology Generation and Beyond

Eng¹,

Lin²,

Chang³

et al. 2011

Jpn. J. Appl. Phys.

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This paper presents a three-dimensional (3D) simulation study of source/drain (S/D)-tied (SDT) double-gate (DG) fin field-effect transistor (FinFET) design for 16-nm half-pitch technology generation and beyond using technology computer-aided design (TCAD) tools. A simple process to fabricate the proposed SDT FinFET is proposed. An investigation of the fin width (W fin) on the electrical characteristics is shown, suggesting that a reduced W fin is good for both the suppression of short-channel effects and the reduction of parasitic capacitance in SDT FinFETs. Also, the self-heating can be well controlled in our proposed SDT FinFET which is a difficult task for SOI family. The proposed FinFET is also compared with the existing experimental data, showing that the SDT FinFET not only demonstrates desired short-channel characteristics due to its inherent structure advantages (partially insulating oxide under the channel region), but also reduces the costs of device fabrication due to its simple process method and planar-like structure.

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Reliability performance characterization of SOI FinFETs

Claeys

Put

Rafı́

et al. 2009

2009 2nd International Workshop on Electron Devices and Semiconductor Technology

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FinFET devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling CMOS to 22 nm and below. Some physical characterization and reliability aspects of these devices are reviewed. Attention is given to transient floating body effects and low frequency noise, which may yield information on the materials' characteristics like carrier recombination lifetime or interface and oxide trap density. These methods can be useful to study the performance of these components under harsh operation conditions of low or high temperature, or at high bias voltages.

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Parasitic S/D resistance effects on hot-carrier reliability in body-tied FinFETs

Cited by 13 publications

References 11 publications

Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions

Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions

A Three-Dimensional Simulation Study of Source/Drain-Tied Double-Gate Fin Field-Effect Transistor Design for 16-nm Half-Pitch Technology Generation and Beyond

Reliability performance characterization of SOI FinFETs

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