Packetization and routing analysis of on-chip multiprocessor networks

Ye, Terry Tao; Benini, Luca; Micheli, Giovanni De

doi:10.1016/j.sysarc.2003.07.005

Cited by 105 publications

(46 citation statements)

References 25 publications

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“…The circular buffer is used to store the incoming packets.Circular buffer system is used to optimize the buffering process [13]. The circular buffer is useful for storing the incoming packets and transferring it to the destination, as illustrated in Fig.…”

Section: Design Of Docket-noc Routermentioning

confidence: 99%

Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC

Vijayaraj¹,

Balamurugan²

2016

JSTS:Journal of Semiconductor Technology and Science

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Section: Design Of Docket-noc Routermentioning

confidence: 99%

Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC

Vijayaraj¹,

Balamurugan²

2016

JSTS:Journal of Semiconductor Technology and Science

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“…2-D mesh topology is one of the most practical and extensively used network topologies [31][32][33][34][35] because of its regularity, simple addressing scheme, and multiple source-destination routes [31]. In this mode, packets are divided into flits, which are the smallest unit of flow control and are equal to the network channel width, excluding flit headers, as shown in Fig.…”

Section: Noc-based Test Platformmentioning

confidence: 99%

Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs

Ansari¹,

Kim²,

Jung³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.

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“…A detailed comparison of several architectures is presented in [5], [6]. As previously discussed, the 2D-mesh proposed in [2] is the most popular.…”

Section: Related Workmentioning

confidence: 99%

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

Bourduas

Žilić

2007

First International Symposium on Networks-on-Chip (NOCS'07)

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Abstract-A popular network topology for Network-on-Chip (NoC) implementations is the two-dimensional mesh. A disadvantage of the mesh topology is in its large communication radius. By partitioning a two-dimensional mesh into several sub-meshes and connecting them using a global interconnect, we can reduce the average number of hops for global traffic. This paper presents a hybrid architecture that partitions a large 2D-mesh into several smaller sub-meshes which are globally connected using a hierarchical ring interconnect. Hierarchical rings have been selected for study because of their simplicity, speed and efficiency in embedding onto a circuit layout, as well as for their suitability for efficient cache coherent protocols. An original SystemC modeling platform was implemented in order to compare the traditional 2D-mesh with the hybrid ring/mesh architectures and the simulation results will show that our hybrid architecture does indeed have a positive effect on the average hop count.

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Packetization and routing analysis of on-chip multiprocessor networks

Cited by 105 publications

References 25 publications

Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC

Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC

Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

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