Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs

Abstract

Abstract-Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.

ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

“…Here, NoC partitioning difficulty is formulated with dynamic programming. In [16], the hybrid test data transportation system for advanced NoC based SoC is described. As the schedule is affected by the location of the access point and the position of the embedded core, a new technique is developed here for concurrently testing several different cores.…”