Abstract-A popular network topology for Network-on-Chip (NoC) implementations is the two-dimensional mesh. A disadvantage of the mesh topology is in its large communication radius. By partitioning a two-dimensional mesh into several sub-meshes and connecting them using a global interconnect, we can reduce the average number of hops for global traffic. This paper presents a hybrid architecture that partitions a large 2D-mesh into several smaller sub-meshes which are globally connected using a hierarchical ring interconnect. Hierarchical rings have been selected for study because of their simplicity, speed and efficiency in embedding onto a circuit layout, as well as for their suitability for efficient cache coherent protocols. An original SystemC modeling platform was implemented in order to compare the traditional 2D-mesh with the hybrid ring/mesh architectures and the simulation results will show that our hybrid architecture does indeed have a positive effect on the average hop count.
This paper describes the modeling and optimization of a hierarchical ring interconnect for system-on-chip multiprocessors. We have selected hierarchical rings for study because they exhibit properties which lend themselves to efficient SoC interconnects. Using our model, we are able to tune certain design parameters in order to reduce energy consumption. We also use dynamic clock throttling which efficiently reduces the energy consumption of the interconnect without adversely affecting system performance.
Use cases are useful in various stages of the software process. They are very often described using text that has to be interpreted by system designers. This could lead to implementation errors. Another drawback of using such informal notations is that automating the process of moving from use cases to design specification is difficult, if not impossible. It would be beneficial to represent use cases in an unambiguous way, thereby reducing the probability of misunderstanding and allowing for automation of various activities in the software process. Message Sequence Charts (MSC) is a formal language and widely used in telecommunications for the specification of the required behaviors. In this paper, we use MSC for describing use cases and we propose an approach for stepwise refinement from high-level use cases in MSC to design MSCs that contain more details about the internal components of the system and their interactions. The refinement steps are done by the designer and guided by the system architecture. For each step, the newly obtained MSC is validated automatically against the previous MSC using a conformance relation between MSCs. Distributed software systems, like any software system, go through requirement, design, implementation and testing phases. Ensuring the quality of such software systems from the initial stages is a challenging task. UML use cases are becoming the standard form for requirements specification. An UML use case describes some functionality offered by a system as perceived by the user or an external actor of the system [1, 2, 9]. The user sees the system as a black box that responds to inputs with a specified output. Use cases are very often specified using a combination of text and diagrams that must be interpreted by the system designers and translated into a more concrete representation. It would be beneficial to represent use cases in an unambiguous way from the start, thereby reducing the probability of misunderstanding, and enabling the use of tools. MSC [3, 4, 11] is an excellent candidate as discussed in [10].
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