Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing

Bourduas, S.; Žilić, Željko

doi:10.1109/asap.2007.4429997

Cited by 13 publications

(7 citation statements)

References 13 publications

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“…A novel interconnect topology called spidergon was proposed in [21], where each core is connected to the clockwise, counterclockwise and diagonal node. A traditional wormhole-routed mesh augmented by a hierarchical ring interconnect for routing global traffic is illustrated in [11]. NOVA is a hybrid interconnect topology targeted at FPGA and is compared in [12] with star, torus and hypercube topologies.…”

Section: Related Workmentioning

confidence: 99%

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Ludovici

Gaydadjiev

Gilabert

et al. 2010

Proceedings of the Third International Workshop on Network on Chip Architectures

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Nowadays, system designers have adopted Networks-on-Chip as communication infrastructure of general-purpose tile-based Multi-Processor System-on-Chip (MPSoC). Such decision implies that a certain topology has to be selected to efficiently interconnect many cores on the chip. To ease such a choice, the networking literature offers a plethora of works about topology analysis and characterization for the off-chip domain. However, theoretical parameters and many intuitive assumptions of such off-chip networks do not necessarily hold when a topology is laid out on a 2D silicon surface. This is due to the distinctive features of silicon technology design pitfalls. This work is a first milestone to bridge this gap, in fact, we propose a comprehensive analysis framework to assess k-ary n-mesh and C-mesh topologies at different level of abstractions, from system to layout level, while capturing implications of system and layout parameters across design hierarchy. When a certain topology proves to be slow due to long links crossing the chip, pipeline stages have been inserted to cope with such slow-down. Furthermore, costs of such speed-up technique have been evaluated to draw a comprehensive performance/area figure.The gap between the constraints driving the design of onchip vs. off-chip interconnection networks (and hence the gap between the final network architectures selected for use in each domain) is increasingly widening even more as an effect of the relentless pace of technology scaling to the nanoscale regime. New physical effects come into play and may either degrade performance/power in an unpredictable way or even affect feasibility of the design at hand or of specific architecture design techniques.Examples concern the large buffering cost associated with techniques borrowed from the off-chip domain (e.g., for congestion management strategies or for deadlock-free and multicast friendly switching mechanisms) which are not affordable in the on-chip domain. Moreover, the interconnect reverse scaling is making designs for on-chip integration increasingly interconnect-dominated, due to the delay associated with the shrinking cross-section area of on-chip interconnects. This effect becomes increasingly severe at each technology node and tends to widen the gap between post-synthesis and postplace&route performance figures and even to move critical path delays from logic blocks to large global wires.Selection of the topology connectivity pattern in the early stages of network design is a decision which is extremely sensitive to both the effects illustrated above. In fact, topologies for on-chip networks must match the 2D silicon surface, while off-chip realizations are dictated by board/rack organization. The 2D mapping constraint raises implementation issues such as wire crossings, wires of uneven length or the decrease of switch operating frequency with the number of I/O ports. As an ultimate consequence, topologies borrowed from off-chip networks should be reassessed in the on-chip environment and validated against...

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Section: Related Workmentioning

confidence: 99%

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Ludovici

Gaydadjiev

Gilabert

et al. 2010

Proceedings of the Third International Workshop on Network on Chip Architectures

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“…Other schemes, such as the adaptive odd-even [8], [12] and adaptive selection nodeon-path (NoP) [13], also provide routing adaptability but only exploit local traffic or conditions of neighbors. There is a great potential to improve communication efficiency by considering the global traffic at runtime using adaptive routing, such as global traffic monitoring [19] and adaptive global routing [20]. However, these approaches employ either a rule-based approach or heuristics for traffic adaptation.…”

Section: A Routing In Nocmentioning

confidence: 99%

Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network

Mak

Cheung

Lam

et al. 2011

IEEE Trans. Ind. Electron.

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Abstract-Dynamic routing is desirable because of its substantial improvement in communication bandwidth and intelligent adaptation to faulty links and congested traffic. However, implementation of adaptive routing in a network-on-chip system is not trivial and is further complicated by the requirements of deadlock-free and real-time optimal decision making. In this paper, we present a deadlock-free routing architecture which employs a dynamic programming (DP) network to provide on-the-fly optimal path planning and network monitoring for packet switching. Also, a new routing strategy called k-step look ahead is introduced. This new strategy can substantially reduce the size of routing table and maintain a high quality of adaptation which leads to a scalable dynamic-routing solution with minimal hardware overhead. Our results, based on a cycle-accurate simulator, demonstrate the effectiveness of the DP network, which outperforms both the deterministic and adaptive-routing algorithms in average delay on various traffic scenarios by 22.3%. Moreover, the hardware overhead for DP network is insignificant, based on the results obtained from the hardware implementations.

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“…Let pi be the i th trial tasks assignment. Its associated schedule cost fcomm is given by (8) where cn, n = 1, ..., N are communication links in pi, and σ is its priority.…”

Section: Noc Communication Optimizationmentioning

confidence: 99%

“…Firstly, we have previously implemented a utility called gengraph that we have used in [7], [8] to generate task graphs. Second, we have implemented a simulated annealing application in C++.…”

Section: Simulation Environmentmentioning

confidence: 99%

Blocking-aware task assignment for wormhole routed network-on-chip

Bourduas

Chan

Žilić

2007

2007 IEEE Northeast Workshop on Circuits and Systems

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Wormhole routed mesh networks can suffer from blocking due to contention when multiple packets are routed along the same path. This paper presents a new method that accounts for blocking and assigns tasks to nodes in a way that tries to minimize contention and thus reduce the latencies introduced by blocking using simulated annealing. We have implemented a xy routed wormhole mesh in SystemC that enables us to evaluate the effectiveness of our methodology. Results show that our methodology is effective at reducing blocking costs and latencies when compared to minimizing communication distances only.

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Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing

Cited by 13 publications

References 13 publications

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology

Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network

Blocking-aware task assignment for wormhole routed network-on-chip

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