A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

Bourduas, S.; Žilić, Željko

doi:10.1109/nocs.2007.3

Cited by 81 publications

(39 citation statements)

References 20 publications

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“…For future scalability independently of the BEE3 architecture, we decided to implement a ring structure. Such rings have already proven useful in multichip systems internally using NoCs [14].…”

Section: Multidevice Architecturementioning

confidence: 99%

A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

Mühlbach

Koch

2012

International Journal of Reconfigurable Computing

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Malicious software has become a major threat to computer users on the Internet today. Security researchers need to gather and analyze large sample sets to develop effective countermeasures. The setting of honeypots, which emulate vulnerable applications, is one method to collect attack code. We have proposed a dedicated hardware architecture for honeypots which allows both highspeed operation at 10 Gb/s and beyond and offers a high resilience against attacks on the honeypot infrastructure itself. In this work, we refine the base NetStage architecture for better management and scalability. Using dynamic partial reconfiguration, we can now update the functionality of the honeypot during operation. To allow the operation of a larger number of vulnerability emulation handlers, the initial single-device architecture is extended to scalable multichip systems. We describe the technical aspects of these modifications and show results evaluating an implementation on a current quad-FPGA reconfigurable computing platform.

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Section: Multidevice Architecturementioning

confidence: 99%

A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

Mühlbach

Koch

2012

International Journal of Reconfigurable Computing

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“…A combination of bus and mesh was used in the NUCA cache and evaluated for an 8-core CMP and a network size of up to 32 nodes. In [21], the authors have proposed a hybrid topology, where they have broken a larger mesh into smaller sub-meshes and used a hierarchical ring as the global network. Their motivation was to decrease the global hop count and reduce congestion at the center of a large mesh.…”

Section: Related Workmentioning

confidence: 99%

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

Das

Eachempati

Mishra

et al. 2009

2009 IEEE 15th International Symposium on High Performance Computer Architecture

168

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Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Both these parameters can also be optimized by application induced communication locality since applications mapped on a large CMP system will benefit from clustered communication, where data is placed in cache banks closer to the cores accessing it. Thus, in this paper, we design a hierarchical network topology that takes advantage of such communication locality. The two-tier hierarchical topology consists of local networks that are connected via a global network. The local network is a simple, high-bandwidth, low-power shared bus fabric, and the global network is a low-radix mesh. The key insight that enables the hybrid topology is that most communication in CMP applications can be limited to the local network, and thus, using a fast, low-power bus to handle local communication will improve both packet latency and power-efficiency. The proposed hierarchical topology provides up to 63% reduction in energy-delayproduct over mesh, 47% over flattened butterfly, and 33% with respect to concentrated mesh across network sizes with uniform and non-uniform synthetic traffic. For real parallel workloads, the hybrid topology provides up to 14% improvement in system performance (IPC) and in terms of energy-delay-product, improvements of 70%, 22%, 30% over the mesh, flattened butterfly, and concentrated mesh, respectively, for a 32-way CMP.Although the hybrid topology scales in a power-and bandwidthefficient manner with network size, while keeping the average packet latency low in comparison to high radix topologies, it has lower throughput due to high concentration. To improve the throughput of the hybrid topology, we propose a novel router microarchitecture, called XShare, which exploits data value locality and bimodal traffic characteristics of CMP applications to transfer multiple small flits over a single channel. This helps in enhancing the network throughput by 35%, providing a latency reduction of 14% with synthetic traffic, and improving IPC on an average 4% with application workloads.

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“…Ainsworth et al [2] study the interconnect architecture of the Cell processor using conventional latency and throughput characterization methods. Bourduas et al [9] explore using a hierarchy of submeshes connected by a global ring interconnect in an effort to decrease the average hop count for global traffic. Many of these studies focus primarily on latency and bandwidth characteristics of on-chip networks.…”

Section: Related Workmentioning

confidence: 99%

Towards scalable, energy-efficient, bus-based on-chip networks

Udipi

Muralimanohar

Balasubramonian

2010

HPCA - 16 2010 the Sixteenth International Symposium on High-Performance Computer Architecture

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A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

Cited by 81 publications

References 20 publications

A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

Towards scalable, energy-efficient, bus-based on-chip networks

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