Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

Das, Reetuparna; Eachempati, Soumya; Mishra, Asit K.; Narayanan, Vijaykrishnan; Das, Chita R.

doi:10.1109/hpca.2009.4798252

Cited by 164 publications

(95 citation statements)

References 24 publications

(38 reference statements)

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“…We assume that the traffic pattern is nonuniform/localized (x) [8]. Let us denote the local traffic percentage that each node of the mesh sends (uniformly) to its immediate neighboring nodes by x.…”

Section: B the Division Ratiomentioning

confidence: 99%

An Efficient Network-on-Chip Architecture Based on Isolating Local and Non-Local Communications

Akhlaghi¹,

Kamal²,

Afzali-Kusha³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-In this paper, we propose a scheme for reducing the latency of packets transmitted via on-chip interconnect network in MultiProcessor Systems on Chips (MPSoCs). In this scheme, the network architecture separates the packets transmitted to near destinations from those transmitted to distant ones by using two network layers. These two layers are realized by dividing the channel width among the cores. The optimum ratio for the channel width division is a function of relative significances of the two types of communications. Simulation results indicate that for non-uniform traffic constituting of more than 30 percent local traffic, the proposed network, on average provides 64% and 70% improvement over the conventional one in terms of average network latency and Energy-Delay product (EDP), respectively. Also, for uniform and NED traffic patterns, by adjusting the number of hops between local nodes to include approximately 55 percent of total communications in local ones, the proposed architecture provides the latency reduction of 50%.

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Section: B the Division Ratiomentioning

confidence: 99%

An Efficient Network-on-Chip Architecture Based on Isolating Local and Non-Local Communications

Akhlaghi¹,

Kamal²,

Afzali-Kusha³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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“…Simulation results show that the BENoC provides an execution speedup around 3× on average compared to a classic NoC. Das et al [2009] proposed a hierarchical hybrid on-chip interconnect that uses both buses and a NoC. Eight PEs are connected by a bus to form a local network.…”

Section: Mixed Architectures Hybrid Interconnectmentioning

confidence: 99%

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Pham‐Quoc¹,

Heisswolf²,

Werner³

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and are thus more energy efficient and have higher performance than general purpose processors, while still providing a large degree of flexibility. However, system performance dose not scale when increasing the number of processing cores due to the communication overhead which increases greatly with the increasing number of cores. Although data communication is a primary anticipated bottleneck for system performance, the interconnect design for data communication among the accelerator kernels has not been well addressed in hardware accelerator systems. A simple bus or shared memory is usually used for data communication between the accelerator kernels. In this dissertation, we address the issue of interconnect design for heterogeneous hardware accelerator systems.Evidently, there are dependencies among computations, since data produced by one kernel may be needed by another kernel. Data communication patterns can be specific for each application and could lead to different types of interconnect. In this dissertation, we use detailed data communication profiling to design an optimized hybrid interconnect that provides the most appropriate support for the communication pattern inside an application while keeping the hardware resource usage for the interconnect minimal. Firstly, we propose a heuristicbased approach that takes application data communication profiling into account to design a hardware accelerator system with a custom interconnect. A number of solutions are considered including crossbar-based shared local memory, direct memory access (DMA) supporting parallel processing, local buffers, and hardware duplication. This approach is mainly useful for embedded system where the hardware resources are limited. Secondly, we propose an automated hybrid interconnect design using data communication profiling to define an optimized interconnect for accelerator kernels of a generic hardware accelerator system. The hybrid interconnect consists of a network-on-chip (NoC), vii viii ABSTRACT shared local memory, or both. To minimize hardware resource usage for the hybrid interconnect, we also propose an adaptive mapping algorithm to connect the computing kernels and their local memories to the proposed hybrid interconnect. Thirdly, we propose a hardware accelerator architecture to support streaming image processing. In all presented approaches, we implement the approach using a number of benchmarks on relevant reconfigurable platforms to show their effectiveness. The experimental results show that our approaches not only improve system performance but also reduce overall energy consumption compared to the baseline systems.

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“…[18] shows that ６ connecting small buses with mesh topology can be effective when it is to be used under traffic with mostly locally-destined packets. [19] uses mesh and ring together to separate control and data packets.…”

Section: Related Workmentioning

confidence: 99%

Tree-Mesh Heterogeneous Topology for Low-Latency NoC

Han

Lee

Choi

2014

Proceedings of the 2014 International Workshop on Network on Chip Architectures

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Tree-Mesh Heterogeneous Topology forLow-Latency NoC SUNGJU HAN DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING COLLEGE OF ENGINEERING SEOUL NATIONAL UNIVERSITYIn Network-on-Chip (NoC), topology is one of the most important design choices that determine performance and power consumption. Mesh, being the most popular NoC topology for many researches and products, is mainly tailored towards high throughput. However, many researches show that NoCs rarely operate under heavy load and that latency is often much more critical in practice. In this paper, I show that by adding a small tree network to assist the baseline mesh network, the zero-load latency can be greatly reduced while still maintaining the high throughput. For the management of the hybrid network, I propose a novel algorithm to steer each packet to different networks based on hop-count gain. The algorithm also includes latency ii monitoring scheme and contention monitoring scheme in order to prevent tree network to get contested too much. Experiments were performed not only on synthetic traffics but also on real application workloads to evaluate the performance of the proposed design. The results show improvements on zero-load latency, throughput, and moreover, energy consumption.

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Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs

Cited by 164 publications

References 24 publications

An Efficient Network-on-Chip Architecture Based on Isolating Local and Non-Local Communications

An Efficient Network-on-Chip Architecture Based on Isolating Local and Non-Local Communications

Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

Tree-Mesh Heterogeneous Topology for Low-Latency NoC

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