Overview and outlook of through‐silicon via (TSV) and 3D integrations

Abstract

Purpose -The purpose of this paper is to focus on through-silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented. Design/methodology/approach -This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for highpower, high-performance, high pin-count, ultra fine-pitch, small real-estate, and low-cost applications. To achieve this, the design uses chip-to-chip interconnections through a passive TSV interposer in a 3D IC integration system-in-package (SiP) format with excellent thermal management. Findings -A generic, low-cost and thermal-enhanced 3D IC integration SiP with a passive interposer has been proposed for high-performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3D IC integration have been presented and discussed. Some important results and recommendations are summarized: the TSV/redistribution layer (RDL)/integrated passive devices passive interposer, which supports the high-power chips on top and low-power chips at its bottom, is the gut and workhorse of the current 3D IC integration design; with the passive interposer, it is not necessary to "dig" holes on the active chips. In fact, try to avoid making TSVs in the active chips; the passive interposer provides flexible coupling for whatever chips are available and/or necessary, and enhances the functionality and possibly the routings (shorter); with the passive interposer, the TSV manufacturing cost is lower because the requirement of TSV manufacturing yield is too high (.99.99 percent) for the active chips to bear additional costs due to TSV manufacturing yield loss; with the passive interposer, wafer thinning and thin-wafer handling costs (for the interposer) are lower because these are not needed for the active chips and thus adds no cost due to yield loss; with the current designs, all the chips are bare; the packaging cost for individual chips is eliminated; more than 90 percent of heat from the 3D IC integration SiP is dissipated from the backside of high-power chips using a thermal interface material and heat spreader/sink; the appearance and footprint of current 3D IC integration SiP designs are very attractive to integrated device manufactures, original equipment manufactures, and electronics manufacturing services (EMS) because they are standard packages; and underfills between the copper-filled TSV interposer and the high-and low-power chips are recommended to reduce creep damage of the lead-free microbump solder joints and prolong their lives. Originality/value -The paper's findings will be very useful to the electronic industry.

Modeling and simulation for the thermo -mechanical interfacial reliability of throug h-silicon-via for 3D IC integration

“…The failure mechanism of the copper/SiO2 consists of two ingredients: a damage initiation criterion and a damage evolution law. Degradation of the cohesive response begins when the maximum nominal strain ratio in the cohesive element attached to the copper and SiO2 dielectric layer reaches a value of one as shown in Equation (1). Once the initiation criterion is reached, the damage evolution law is used to describe the rate at which the cohesive stiffness is degraded as shown in Fig 5. To define the damage evolution of the interface cohesive response based on energy, the energy dissipated due to failure should be known and the degradation behavior is assumed to obey exponential softening law.…”

“…Through silicon via (TSV) is supposed to be the most promising substitute for conventional wire bonding in 3D IC integration due to its many advantages [1]- [3]. Comparatively, the TSV based interconnecting approach may have more reliability problems which have not been well understood yet, and may hamper its further development in the practice applications.…”

Analysis of encapsulation process in 3D stacked chips with different microbump array

“…Despite all the benefits in 3D system integration with TSV, as mentioned by several scholars in the literature [2][3][4], there are still many challenges ahead [5][6][7] before this technology is able to be fully implemented in electronic packages. At the moment, TSV technology is still largely limited to the areas of homogeneous system integration in DRAM, and CMOS image sensors.…”

Thermal fatigue reliability design of solder bumps in TSV interposer package based on finite element analysis

“…Three-dimensional (3D) package based on TSV interposer technology has emerged as a good solution to support and fan out ultra-fine pitch, high I/O counts IC chip to fewer and relatively larger pitch pads on a simpler and thinner BT substrate, realizing smaller footprint with higher performance [1]. However, reliability problems, such as interfacial delamination and fatigue failure could be resulted from the CTE (Coefficient of Thermal Expansion) mismatch between different materials during assembly process or in service [2][3].…”