Modeling and simulation for the thermo -mechanical interfacial reliability of throug h-silicon-via for 3D IC integration

Abstract

To meet the needs of the continual scaling of wiring structures, 3D IC integration with through-silicon-vias has become the most important direction to go for further miniaturization. Compared to the conventional packaging, 3D integration based on the TSV technology has several inherent advantages, such as small size, high density and short interconnect path. Consequently, TSV technology has attracted wide spread interest in the circuits and devices, packaging and testing communities in the world. As the heart and key technology for 3D integration, TSV structures should be sufficiently reliable to guarantee the performance of the packaged devices. Among all the concerned reliability problems, thermo-mechanical interfacial reliability is crucial one which should deserve more attention. In this paper, modeling and simulation has been carried out to examine the impact of the thermal stress on the interfacial reliability of the TSV structures. Firstly, distribution of the thermal stresses and strains of the structure and the interface has been calculated by a thermo-mechanical FEA model. To obtain more appropriate results, the copper filled in the vias was considered to be elastic-plastic. The mechanical elastic property and the coefficients of thermal expansion (CTE) of copper and silicon were considered to be temperature dependent. Subsequently, a damage model was built up to simulate the initiation and propagation of the interfacial crack. Cohesive elements with "traction-separation" response were used in the model. Furthermore, energy release rate associated with interfacial crack growth was calculated and J-integral method for calculation of energy release rate was introduced to investigate the crack growth stability of TSV structures with preexisting cracks. Cases with cracks at different locations and various crack lengths have been simulated. Results indicate that thermal stress may concentrate on the interface with different materials. The stress concentration locations were the potential positions where the crack may be most likely initiated. And the simulation results of the damage model show that the interface crack growth may be unstable and cracks may initiate and propagate as the temperature difference is up to 325℃. And the interface may fail to work rapidly once it is damaged. For the preexisting cracks in the interface, they may propagate if the crack length is long enough. The estimated critical length of notch crack is about 2μm, and 4μm for buried cracks when a temperature difference 255 ℃ is applied on the structure. The energy release rate increases with the crack length. The results further show that the strain energy release rate for notch cracks is higher than the buried ones with the same crack length so that the notch cracks should deserve more attention during the manufacture processes. IntroductionThrough silicon via (TSV) is supposed to be the most promising substitute for conventional wire bonding in 3D IC integration due to its many advantages[1]- [3]. Comparatively, the TSV based int...