Origin of wide retention distribution in 1T Floating Body RAM

Aoulaiche, M.; Nicoletti, T.; Veloso, A.; Roussel, Ph.; Simoen, Eddy; Claeys, Cor; Groeseneken, G.; Jurczak, M.

doi:10.1109/soi.2012.6404394

Cited by 8 publications

(5 citation statements)

References 4 publications

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“…16 shows that similar retention time distributions are obtained for the different type of devices evaluated suggesting similar traps, and generation/recombination (GR) centers distributions. 33) For logic UTBB planar devices (see Fig. 17), the two doping approaches (with and without extensions I/I) yield results in line with those obtained for FinFETs and for 1T-FBRAM UTBB devices.…”

Section: Device Results and Discussionsupporting

confidence: 80%

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Veloso¹,

Keersgieter²,

Aoulaiche³

et al. 2013

Jpn. J. Appl. Phys.

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In this work we explore the use of extension-less doping schemes for fully-depleted devices [two-dimensional (2D): ultra-thin body and buried-oxide layer (BOX) planar devices (UTBB); three-dimensional (3D): multi-gate field-effect transistor devices with the conduction channels wrapped around silicon (Si) fins (FinFETs) and built on bulk-Si or silicon-on-insulator (SOI) substrates], suitable for advanced logic, memory and dense circuit applications. We demonstrate that by using Si epitaxial raised source (S)/drain (D) (SEG) followed by highly doped drain (HDD)-only implantations (I/I), or by using doped-SEG and no I/I: 1) lower off-state current (I OFF) and drain induced barrier lowering effect (DIBL); 2) steeper sub-threshold slope (SS); 3) higher on-state/off-state currents ratio (I ON/I OFF); and 4) higher retention times [for floating body random-access memory (FBRAM) on UTBB] can be obtained, while reducing cost and cycle time with less critical I/I photos. SEG facet formation can be controlled by the spacers shape and epi pre-clean step and its impact on device characteristics for logic and FBRAM applications is also analyzed.

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Section: Device Results and Discussionsupporting

confidence: 80%

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Veloso¹,

Keersgieter²,

Aoulaiche³

et al. 2013

Jpn. J. Appl. Phys.

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“…observed experimentally [21]. More important is that interface states are strongly related, via the trap capture cross-section (σ) dependence with the trap energy [22], with the wide retention time variability observed in capacitorless cells [23], [24]. Since retention time in long Z 2 -FETs is driven by the SRH generation at the anode-body junction [4], reducing the surface recombination velocity negatively impacts this figure of merit.…”

Section: B Retention Timementioning

confidence: 99%

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z²-FETs

Navarro

Vilanova

Márquez

et al. 2019

IEEE Trans. Electron Devices

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3D numerical TCAD simulations, based on experimental results, are performed to study the origin of the large Z 2-FET DRAM memory cell-to-cell variability on FD-SOI technology. The body width, cross-section shape and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated at room temperature. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state (Dit) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON voltage variability threatening the capacitor-less DRAM operation.

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“…A variation of 0.1 eV in the trap energy level in the Si band gap results in a change of about two orders of magnitude difference in the retention time. Moreover, defects closer to the silicon mid-gap can be detrimental for the retention time [28,29]. Fig.…”

Section: Retention Time Distributionmentioning

confidence: 99%

Understanding and optimizing the floating body retention in FDSOI UTBOX

Aoulaiche¹,

Simoen

Caillat³

et al. 2016

Solid-State Electronics

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Origin of wide retention distribution in 1T Floating Body RAM

Cited by 8 publications

References 4 publications

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z²-FETs

Understanding and optimizing the floating body retention in FDSOI UTBOX

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Origin of wide retention distribution in 1T Floating Body RAM

Cited by 8 publications

References 4 publications

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs

Understanding and optimizing the floating body retention in FDSOI UTBOX

Contact Info

Product

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About

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z²-FETs