Optimization of Embedded Compact Nonvolatile Memories for Sub-100-nm CMOS Generations

Akil, N.; Duuren, M. van; Slotboom, M.; Baks, W.; Goarin, P.; Schaijk, R. van; Tello, Pablo G.; Cuppens, R.

doi:10.1109/ted.2005.844760

Cited by 6 publications

(2 citation statements)

References 8 publications

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“…Split-gate flash memory has been widely studied for embedded memory applications thanks to its high programming efficiency, low power consumption and immunity to over-erase problem. [1][2][3][4][5][6][7][8][9][10][11] Source-side injection (SSI) of hot electrons is most commonly utilized to program the cell because both high lateral and vertical field are obtained in the gap region with proper bias. 1) The charge-storage layer of split-gate memory can be floating poly, nitride 9) or nanocrystal.…”

Section: Introductionmentioning

confidence: 99%

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Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory

Zhao¹,

He²,

Huang³

et al. 2010

Jpn. J. Appl. Phys.

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We explore the conjectured duality between the critical O(N) vector model and minimal bosonic massless higher spin (HS) theory in AdS. In the free boundary theory, the conformal partial wave expansion (CPWE) of the four-point function of the scalar singlet bilinear is reorganized to make it explicitly crossing-symmetric and closed in the singlet sector, dual to the bulk HS gauge fields. We are able to analytically establish the factorized form of the fusion coefficients as well as the two-point function coefficient of the HS currents. We insist in directly computing the free correlators from bulk graphs with the unconventional branch. The three-point function of the scalar bilinear turns out to be an "extremal" one at d = 3. The four-point bulk exchange graph can be precisely related to the CPWs of the boundary dual scalar and its shadow. The flow in the IR by Legendre transforming at leading 1/N, following the pattern of double-trace deformations, and the assumption of degeneracy of the hologram lead to the CPWE of the scalar fourpoint function at IR. Here we confirm some previous results, obtained from more involved computations of skeleton graphs, as well as extend some of them from d = 3 to generic dimension 2 < d < 4.

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Section: Introductionmentioning

confidence: 99%

“…1) The charge-storage layer of split-gate memory can be floating poly, nitride 9) or nanocrystal. 11) For split-gate memory cell with floating poly, it can be erased by uniform channel Fowler-Nordheim (FN) erase, 3) source-junction-side FN erase, 2) or poly-topoly FN erase. 5) In ref.…”

Section: Introductionmentioning

confidence: 99%

Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory

Zhao¹,

He²,

Huang³

et al. 2010

Jpn. J. Appl. Phys.

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Highly Reliable Flash Memory with Self-Aligned Split-Gate Cell Embedded into High Performance 65nm CMOS for Automotive & Smartcard Applications

Shum¹,

Power²,

Ullmann³

et al. 2012

2012 4th IEEE International Memory Workshop

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Functionality Demonstration of a High-Density 1.1V Self-Aligned Split-Gate NVM Cell Embedded into LP 40 nm CMOS for Automotive and Smart Card Applications

Shum

Luo

Chow

et al. 2015

2015 IEEE International Memory Workshop (IMW)

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Optimization of Embedded Compact Nonvolatile Memories for Sub-100-nm CMOS Generations

Cited by 6 publications

References 8 publications

Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory

Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory

Highly Reliable Flash Memory with Self-Aligned Split-Gate Cell Embedded into High Performance 65nm CMOS for Automotive & Smartcard Applications

Functionality Demonstration of a High-Density 1.1V Self-Aligned Split-Gate NVM Cell Embedded into LP 40 nm CMOS for Automotive and Smart Card Applications

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Optimization of Embedded Compact Nonvolatile Memories for Sub-100-nm CMOS Generations

Cited by 6 publications

References 8 publications

Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory

Impact of Source Junctions on the Performance and Cycling-Induced Degradation of Split-Gate Flash Memory

Highly Reliable Flash Memory with Self-Aligned Split-Gate Cell Embedded into High Performance 65nm CMOS for Automotive &amp; Smartcard Applications

Functionality Demonstration of a High-Density 1.1V Self-Aligned Split-Gate NVM Cell Embedded into LP 40 nm CMOS for Automotive and Smart Card Applications

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Product

Resources

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Highly Reliable Flash Memory with Self-Aligned Split-Gate Cell Embedded into High Performance 65nm CMOS for Automotive & Smartcard Applications