2018
DOI: 10.1002/solr.201800070
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Optimization of Belt Furnace Anneal to Reduce Light and Elevated Temperature Induced Degradation of Effective Carrier Lifetime of P‐Type Multicrystalline Silicon Wafers

Abstract: Light and elevated temperature induced degradation (LeTID) of the effective charge carrier lifetime significantly lowers the efficiency of multicrystalline silicon (mc-Si) solar cells and is a major challenge currently faced by the silicon photovoltaic industry. Optimization of the temperature profile used in the rapid thermal anneal (RTA) step of the metallization line has been found to significantly reduce LeTID of mc-Si solar cells. Hence, the authors experimentally study the impacts of varying the RTA proc… Show more

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Cited by 10 publications
(8 citation statements)
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“…126 Annealing in the dark has also been shown to suppress LeTID. 41,73,88 Similar to the approach in the belt-furnace, dark annealing has been shown to result in a drop in device FF for longer durations and higher temperatures. 122 To the avoid the drop in device FF, Sen et al 127 proposed a possible alternative method whereby the anneal is performed prior to metal contact firing.…”
Section: Mitigation Of Letidmentioning
confidence: 99%
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“…126 Annealing in the dark has also been shown to suppress LeTID. 41,73,88 Similar to the approach in the belt-furnace, dark annealing has been shown to result in a drop in device FF for longer durations and higher temperatures. 122 To the avoid the drop in device FF, Sen et al 127 proposed a possible alternative method whereby the anneal is performed prior to metal contact firing.…”
Section: Mitigation Of Letidmentioning
confidence: 99%
“…The maximum degradation extent as a function of peak firing temperature for (A) SiN x only passivated symmetrical test structures and (B) structures with at least one side AlO x or Al 2 O 3 passivated with SiN x capping as extracted from previous studies. 12,14,34,[36][37][38][39][40][41] The corresponding legends highlights the various test structures and conditions used. Lower temperatures and unfired wafers have been excluded as they typically show negligible degradation.…”
Section: A Universal Defect In Siliconmentioning
confidence: 99%
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“…Even though no results were published to back this claim, the idea inspired further research. So far, it has been shown that greatly reducing the cooling rate or slowing down the whole firing process by lowering the belt speed reduces LeTID in hpm lifetime samples 18,19 . Only reducing the slope of the cooling ramp has been shown to work on lifetime samples out of conventional mono‐cast material, when reducing the cooling rate to 20 K/s 20 or even up to 50 K/s in p‐type Cz lifetime samples 21 .…”
Section: Introductionmentioning
confidence: 99%