Optimal sequencing energy allocation for CMOS integrated systems

Abstract

All synchronous CMOS integrated systems have to pay some sequencing overhead. This overhead includes the skew and the jitter of the clock. It also includes the setup time and the clock-to-output delay of the flip-flops. This paper discusses how much energy should be allocated for sequencing in these systems. It is pointed out that providing too little energy is just as bad as providing too much. It is also argued that directly trying to minimize the energy-delay product of the sequencing subsystem is practically not the right thing to do. A model for the relationship between supply voltage, clock frequency, and power dissipation is developed and empirically verified for a SPARC V9 microprocessor. An expression for the optimal energy allocation in a system is derived. Then, based on this optimum, a methodology to design energy-efficient systems is proposed.

Clocking and clocked storage elements in a multi-gigahertz environment

“…This can be satisfied with reasonably low hardware overhead. In addition, the clock uncertainty resulting from the variation of the duty cycle can be partially absorbed by the storage element [32]. The two fundamental ways of building dual-edge CSEs are the latch-mux and flip-flop, as shown in Figures 17(a) and 17(b).…”