Clocking and Clocked Storage Elements in Multi-GHz Environment

Oklobdzija, Vojin G.

doi:10.1007/3-540-45716-x_14

Cited by 6 publications

(10 citation statements)

References 15 publications

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“…In full-custom design reducing clock energy is feasible by sharing the pulse generator between different FFs [5]. However, for our replacement strategy this is not possible, because PFFs are placed at fixed positions and thus sharing a pulse generator would complicate the rerouting after FF insertion.…”

Section: A Novel P-ff For Semicustom Design Flowmentioning

confidence: 99%

“…Various FF implementations have already been proposed to reduce the synchronization timing overhead [5,8]. In semicustom design there are additional prerequisites which have to be fulfilled by a FF, e.g.…”

Section: A Novel P-ff For Semicustom Design Flowmentioning

confidence: 99%

“…Employing a P-FF with 0ps setup time still enables late data sampling by exploiting the transparency phase of the P-FF, i.e. the soft clock edge property to enable dynamic time-borrowing [5]. However, independent of the operating point, in path topologies where setup time critical paths and hold time critical paths share the same receiving FF, special attention is required to avoid race conditions.…”

Section: Introductionmentioning

confidence: 96%

See 2 more Smart Citations

Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement

Baumann

Berthold

Niedermeier

et al. 2007

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

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Performance improvement of an ARM926 microprocessor core by selective replacement of standard master-slave flip flops using low-V T flip flops or a novel type of pulsed flip flop (P-FF) is investigated. Different replacement strategies are proposed that are independent of path and pipeline topologies. These strategies are compared to each other concerning performance improvement and costs. For an existing 90nm CMOS design a 5% speed improvement on design level is achieved at low area overhead of 1%. An experimental verification of the proposed concept using a loop of critical paths shows 12% speed increase at 500MHz and V DD =1.2V in a 65nm CMOS technology.

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Section: A Novel P-ff For Semicustom Design Flowmentioning

confidence: 99%

Section: A Novel P-ff For Semicustom Design Flowmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 96%

See 1 more Smart Citation

Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement

Baumann

Berthold

Niedermeier

et al. 2007

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

View full text Add to dashboard Cite

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“…We use the same pulse generator as in [1], [2], [22], [23] (see Figure 3). The pulse signal is produced by ANDing the non-complemented and complemented signals from the clock.…”

Section: Pulse Generatormentioning

confidence: 99%

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms

Mansouri

Dubrova

2010

2010 IEEE International Conference on Computer Design

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In this paper, we address the problem of lowoverhead implementation of Feedback Shift Registers (FSRs). We present a dynamic pulse latch which is based on transistors with two different channel lengths. The channel lengths are selected to make the latch suitable for replacing flip-flops in FSRs. The presented latch is 1.92 times smaller and 3.94 times less power consuming compared to the smallest standard flip-flop in the same technology. By re-implementing FSRs of Grain-80 stream cipher with the presented latch, we achieve 32.24% reduction in area, 36.77% reduction in total power, and 10.81% increase in the maximum clock frequency compared to the original, flipflop based version of Grain-80. If, in addition, the static time borrowing technique is applied, we achieve an additional 25.5% increase in the maximum clock frequency at the expense of 4.68% smaller gain in area and 2.67% smaller gain in total power. 978-1-4244-8935-0/10/$26.00 ©2010 IEEE

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“…From a timing perspective, FF latency consumes a large portion of the clock cycle time while the operating frequency increases. 1 Moreover, in order to sustain the trend of high performance and throughput, a large number of FFs is usually employed for extensive pipelining of datapath sections, causing the power dissipation of FFs having a deep impact on the power characteristics of the whole system. 2 Both master-slave (MS-) and pulsed-triggered (P-) FFs are commonly used in contemporary digital systems.…”

Section: Introductionmentioning

confidence: 99%

A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops

Lanuzza¹

2013

Journal of Low Power Electronics

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In this paper, simple circuital techniques to design efficient pulse triggered flip-flops are presented. The proposed approach aims at considerably alleviating the detrimental effects of current contention mechanisms, occurring at critical switching nodes of the circuits. In this way, both latency and power consumption of pulse triggered flip-flops are reduced. The proposed approach is assessed by means of simulations in 90-nm ST commercial CMOS technology. When applied to some recently proposed implicit pulse triggered flip-flop architectures, the suggested design strategy, allows speed to be improved up to 13% and power-delay-product to be lowered down to 14%. Moreover, also the process variation tolerance is considerably improved.

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Clocking and Clocked Storage Elements in Multi-GHz Environment

Cited by 6 publications

References 15 publications

Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement

Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms

A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops

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