Clocking and clocked storage elements in a multi-gigahertz environment

Abstract

Clocking and clocked storage elements in a multi-gigahertz environment Clocking considerations and the design of clocked storage elements are discussed in this paper. We present a systematic approach for deriving a clocked storage element suitable for "time borrowing" and absorption of clock uncertainties. We explain how to compare different clocked storage elements with each other, and discuss issues related to power consumption and low-power designs. Finally, results of comparisons among representative designs are presented. Clocking considerations in sequential systems Clock distribution The two most important timing parameters that affect the clock signal are clock skew and clock jitter. Clock skew is a spatial variation of the clock signal as distributed through the system. It is caused by the various resistive/capacitive (RC) characteristics of the clock paths to the various points in the system and the different loading of the clock signal at different points on the chip. Further, we can distinguish global clock skew and local

Comparative analysis of yield optimized pulsed flip-flops

“…L min = 40 nm), as common in digital design. The minimum channel width was used for transistors PDF EDP yield = 99.87% 2 FO2 is the slope of the output waveform of an inverter loaded by two inverters of the same size [24]. that do not significantly affect the FF performance (shown as à in Fig.…”

A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure Design

“…Consider the typical TGMS FF shown in Figure.3 introduced in [7].In this modified version PowerPC 603 is mainly used for low-power processor. Here, an inverter is added to isolate the D input and provide better noise immunity.…”

A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors

“…In the meantime, the singlephase pulsed operation reduces latch latency as well as allows time borrowing to enhance frequency performance. The advantage and tradeoff of pulse latches are well documented in [11,12]. While increasing the pulse width is beneficial for the speed, it also increases the minimum bound of the fast paths which requires rigorous padding to avoid early mode failure.…”