Comparative analysis of yield optimized pulsed flip-flops

Lanuzza, Marco; Rose, Raffaele De; Frustaci, Fabio; Perri, Stefania; Corsonello, Pasquale

doi:10.1016/j.microrel.2012.03.024

Cited by 27 publications

(4 citation statements)

References 24 publications

(35 reference statements)

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“…2. Inherent from Domino logic the DML based comparator is also able to perform within a single clock cycle, the signals GGG and GGP are latched [15]- [17], and Post Processing Stage evaluates during the clock low half-cycle. In the static mode the latch is transparent to the clock signal.…”

Section: Dual Mode Logic Based Single-clock-cycle Binary Comparatormentioning

confidence: 99%

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

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Prócel

Trojman³

et al. 2021

2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS)

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This paper presents an energy-efficient singleclock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43% energy consumption compared to the equivalent domino logic-based implementation.

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Section: Dual Mode Logic Based Single-clock-cycle Binary Comparatormentioning

confidence: 99%

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

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Prócel

Trojman³

et al. 2021

2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS)

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“…Consequently, the voltage at the dynamic node of the DL gate and the current I p,DL vary as given in (11) and (12).…”

Section: Ung Variability Modelmentioning

confidence: 99%

“…In the last few years, special efforts have been done by researchers to develop design techniques able to reduce the effects of PV in nanometer digital circuits. Several PV aware design techniques were proposed for both static [3][4][5][6][7] and dynamic circuits [8][9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Analyzing noise robustness of wide fan‐in dynamic logic gates under process variations

Frustaci¹,

Lanuzza²,

Perri³

et al. 2012

Circuit Theory & Apps

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Wide fan‐in dynamic logic gates are difficult to design due to the large number of leaky evaluation paths connected to the dynamic node. Designers have to cope with their low noise tolerance further worsened by the effects of process parameter variation. In this paper, a novel analytical model is derived and validated to evaluate the noise robustness of wide fan‐in dynamic logic gates taking process variation effects into account. Experiments were performed using a commercial 45‐nm 1‐V CMOS technology, and the noise robustness in terms of unity noise gain (UNG) was evaluated for 16 and 32‐bit OR gates. Obtained results demonstrate that the proposed model is able to predict the mean value of the UNG with a maximum error of only 6.8%, whereas the difference between the predicted and simulated UNG yield is always lower than five percentage points. Copyright © 2012 John Wiley & Sons, Ltd.

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“…There main limitations on the speed performance of CMOS static logic gates, especially for high fanin gates, are the large input capacitance and the contention between the PUN and the PDN during the gate switching [10][11][12]. In order to counteract these drawbacks, dynamic domino logic can be used for the design of high-speed data paths [13][14][15][16][17][18], at the expense of higher energy and increased sensibility to process variations [19][20][21][22][23].…”

Section: Introductionmentioning

confidence: 99%

Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder

et al. 2021

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This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode.

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Comparative analysis of yield optimized pulsed flip-flops

Cited by 27 publications

References 24 publications

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Analyzing noise robustness of wide fan‐in dynamic logic gates under process variations

Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder

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