Analyzing noise robustness of wide fan‐in dynamic logic gates under process variations

Abstract

Wide fan‐in dynamic logic gates are difficult to design due to the large number of leaky evaluation paths connected to the dynamic node. Designers have to cope with their low noise tolerance further worsened by the effects of process parameter variation. In this paper, a novel analytical model is derived and validated to evaluate the noise robustness of wide fan‐in dynamic logic gates taking process variation effects into account. Experiments were performed using a commercial 45‐nm 1‐V CMOS technology, and the noise robustness in terms of unity noise gain (UNG) was evaluated for 16 and 32‐bit OR gates. Obtained results demonstrate that the proposed model is able to predict the mean value of the UNG with a maximum error of only 6.8%, whereas the difference between the predicted and simulated UNG yield is always lower than five percentage points. Copyright © 2012 John Wiley & Sons, Ltd.

Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

“…So the most obvious and the simplest way of power reduction would be to reduce V DD . But the downside is that the lower V DD degrades performance and makes the circuit highly prone to manufacturing variations and to noise .…”