Conditional pre-charge techniques for power-efficient dual-edge clocking

Abstract. An analysis of the efficiency of power-gating for Clocked Storage Elements (CSEs) is presented. Two CSE topologies: the Transmission Gate Master Slave latch (TGMS) and the Write Port Master Slave latch (WPMS) are examined along with their respective circuits with sleep transistors. In this work, we study the benefits of adding sleep transistors coupled with regular clock-gating during inactive mode. We examine the energy savings for standard clock gated CSEs versus their power gated counterparts. This is done by studying how the leakage energy saved with power gating offsets the energy consumed by the extra transistors added to support it. It is not always beneficial to add sleep transistors when deciding between power-gating or just using clockgating. We also study how the results and tradeoff change with voltage scaling.

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RETRACTED: FPGA based design and implementation of low power dual edge triggered flipflop using dynamic signal driving scheme for memory applications

Punitha¹,

Sundararajan

2020

Microprocessors and Microsystems

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Conditional pre-charge techniques for power-efficient dual-edge clocking

Cited by 5 publications

References 10 publications

Clocking and Clocked Storage Elements in Multi-GHz Environment

Clocking and Clocked Storage Elements in Multi-GHz Environment

Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements

RETRACTED: FPGA based design and implementation of low power dual edge triggered flipflop using dynamic signal driving scheme for memory applications

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