This paper represents a departure from the conventional methods of design and analysis of clocked storage elements that rely on minimizing a fixed energy-delay metric. Instead it establishes a systematic comparison in the energy-delay design space based on the parameters of the surrounding blocks. We define the composite energy-efficient characteristic over all storage element topologies and identify the most efficient storage element depending on its position on the composite characteristic relative to other topologies within a pipeline stage. Thus, we show that an optimal design could use a mixed variety of clocked storage elements (CSEs) depending on their placement in the pipeline and critical path. Since a well-designed system has hardware intensities balanced for a given cycle, a CSE choice will be made depending on the pipeline and path intensities. We show that a meaningful comparison can be carried out only by acknowledging that the optimal design and choice of the clocked storage elements depends heavily on the application, and by analyzing the energy and delay of the clocked storage elements in context of this application. The analysis in the energy-delay space allows us to understand some intuitive design choices in a quantitative way and to identify the optimal storage element topologies for an arbitrary system specification.
Abstract. An analysis of the efficiency of power-gating for Clocked Storage Elements (CSEs) is presented. Two CSE topologies: the Transmission Gate Master Slave latch (TGMS) and the Write Port Master Slave latch (WPMS) are examined along with their respective circuits with sleep transistors. In this work, we study the benefits of adding sleep transistors coupled with regular clock-gating during inactive mode. We examine the energy savings for standard clock gated CSEs versus their power gated counterparts. This is done by studying how the leakage energy saved with power gating offsets the energy consumed by the extra transistors added to support it. It is not always beneficial to add sleep transistors when deciding between power-gating or just using clockgating. We also study how the results and tradeoff change with voltage scaling.
A low power circuit design strategy is presented. We believe this methodology can be used to develop fast and inexpensive techniques to aid designers in power optimizations which are generally compute time hungry. The design strategy explored allows for fast sizing of the circuit to get to within 5% of an optimal operating point in terms of energy. Traditional optimization for energy uses time consuming, exhaustive simulations to determine the best possible operating point. The design rules being developed aim to predict the energy optimal point with accuracy but more importantly assist designers to arrive at a minimum energy solution quickly and explore design options better. Furthermore these rules can be used to develop optimization tools which are several orders of magnitude faster than current linear programming and convex optimization tools.
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