The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements

Abstract

This paper represents a departure from the conventional methods of design and analysis of clocked storage elements that rely on minimizing a fixed energy-delay metric. Instead it establishes a systematic comparison in the energy-delay design space based on the parameters of the surrounding blocks. We define the composite energy-efficient characteristic over all storage element topologies and identify the most efficient storage element depending on its position on the composite characteristic relative to other topologies within a pipeline stage. Thus, we show that an optimal design could use a mixed variety of clocked storage elements (CSEs) depending on their placement in the pipeline and critical path. Since a well-designed system has hardware intensities balanced for a given cycle, a CSE choice will be made depending on the pipeline and path intensities. We show that a meaningful comparison can be carried out only by acknowledging that the optimal design and choice of the clocked storage elements depends heavily on the application, and by analyzing the energy and delay of the clocked storage elements in context of this application. The analysis in the energy-delay space allows us to understand some intuitive design choices in a quantitative way and to identify the optimal storage element topologies for an arbitrary system specification.

Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements

“…The TGMS is a conventional master-slave latch topology in which both master and slave latches are implemented with transmission gates [1]. It is used in the Power PC 603 low-power processor [12], and it is generally considered as a low power [14]. The WPMS works also like a master-slave structure.…”

“…The results presented in this section and section 5 were obtained by using HSPICE and 65nm CMOS technology models [17]. The setup, similar to the one used by [3] [14], was used for the simulation of the individual CSEs during active mode. Fig.…”

“…Several methods have been developed to reduce the active energy of flipflops [1][2] [15] [16]. However, in our analysis we will focus on leakage control methodologies on Master-Slave latch structures since these topologies are the most energy efficient in low power designs [14]. Circuit-level approaches to leakage power reduction include Multi-Threshold CMOS (MTCMOS) [6] [7] and power-gating [8][9] [10].…”

A Novel Flipflop Topology for High Speed and Area Efficient Logic Structure Design

“…An LE approach is used only when flipflops are in critical path its small output delay can be optimized with its circuit speed [5]. This method is useful for designers to calculate the speed performances of a circuit.…”

“…LE optimization is carried on by looking at the whole circuit as a unique uninterrupted path [1].The problem of delay minimization has to be looked at from a different perspective by resorting to a novel approach, which gets inspiration from preliminary considerations [5]. TGMS FFs are split into two overlapping sections and two different paths that are separately optimized [10].…”