Design in the Energy–Delay Space

Flip-Flop Design in Nanometer CMOS

“…In the following, a model accounting for the above contributions is summarized [7,8]. This model aims at the extraction of a factor v featuring a logic gate and such that the overall gate energy E is simply expressed as linearly related to the input capacitance C IN , i.e.…”

“…2.1), and it is assumed that each transistor contributes with a single gate and a single parasitic capacitance. 1 In order to include the parasitic capacitances due to local interconnects (within the logic gate) at the input and the output of the gate, let us introduce parameters z in and z out that weigh 2 parasitic capacitive contributions through the gate size w. Hence, the overall local wire capacitance C par;j at a generic node j can be expressed as [7,8] …”

“…As concerns parameter c in (2.11) and the actual analytical expression of the EEC under our assumption, analytical calculations can be carried out only for a single logic gate [7,8]. Indeed, according to Logical Effort model, one has…”

“…Accordingly, the analytical interpretation of hardware intensity is related to the energy-to-delay sensitivity evaluated in correspondence of the design points optimizing the E i D j (ED g ) metrics [7,8,157,158]. Indeed, the design point minimizing E i D j for a given i; j ð Þ leads to a zero derivative of E i D j with respect to D and E [7,8,119] …”

“…Indeed, the design point minimizing E i D j for a given i; j ð Þ leads to a zero derivative of E i D j with respect to D and E [7,8,119] …”