Flip-Flop Design in Nanometer CMOS

Alioto, Massimo; Consoli, Elio; Palumbo, G.

doi:10.1007/978-3-319-01997-0

Cited by 14 publications

(8 citation statements)

References 118 publications

(439 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1(b) and evaluating best case, worst case and average case. Switching activity minimized in different state of art papers utilizing various dynamic power reduction techniques at circuit level design abstraction included clock gating, sleep transistors method and forced stack transistor technique [12][13][14][15]. Clock gating is used to reduce dynamic power and illustrate the effect of switching activity on total power consumption of a digital synchronous design.…”

Section: Investigation Of Sense Amplifier Based Single Edge Trigger D...mentioning

confidence: 99%

“…2(d), represented a new slave latch that removes the problems faced by Kim and maintaining the profits of the same. This new slave architecture requires twelve transistors and it was a mixed solution which was obtained from NAND-based SR latch [11,21,25] and the C2MOS design [15]. Now, sense amplifier based D flip flop designs have been discussed below in detail and further compared with proposed designs.…”

Section: Investigation Of Sense Amplifier Based Single Edge Trigger D...mentioning

confidence: 99%

“…Still, LPSAFF required a lot of improvement at slow working NAND based D latch circuitry. A variety of slave latch structures for low power SAFF are explored [15][16][17][18][19][20][21][22][23][24][25]. A modified latch design introduced by Nikolic is explained in [21].…”

Section: Low Power Sense Amplifier Flip Flop (Lpsaff)mentioning

confidence: 99%

See 2 more Smart Citations

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Swami

Sharma²

2022

Silicon

View full text Add to dashboard Cite

Energy conservation and delay minimization are the two major goals while designing ultra-low-power digital integrated circuits at lower technology nodes. Here, silicon based carbon nanotube field effect transistor (CNTFET) has been explored as a novel material for future electronics design applications (EDA). In this paper, two energy-efficient switching activity minimization techniques have been applied with proposed designs. First technique detects the completion of sensing stage operation known as transition completion detection (TCD) technique. TC signal generated from NAND operation of complementary outputs of sensing stage which minimizes glitches in the complementary outputs of the latch stage. Another clock gating mechanism applied at the latch stage to smoothen the output waveforms Q and Q. The proposed and existing designs simulated using 32nm CMOS and 32nm CNT-FET technology, indicating that the CNTFET based design reduces power by 45% and 36% respectively in comparison with conventional CMOS. Proposed Low Power Sense Amplifier Flip Flop with transition control detection (TCD-LPSAFF) and Ultra Low Energy Sense Amplifier Flip Flop (ULESAFF) give minimal power delay product (PDP) which is 35.7 × 10 −18 J and 29.6 × 10 −18 J respectively. Also, the effect of process variation has been analyzed at specified corners (FF, TT and SS) in the temperature range of -40 • C to 120 • C. The performance of all designs has been validated by functionality testing with variation in load cpacitance, diameter, number of tubes and pitch respectively.

show abstract

Section: Investigation Of Sense Amplifier Based Single Edge Trigger D...mentioning

confidence: 99%

Section: Investigation Of Sense Amplifier Based Single Edge Trigger D...mentioning

confidence: 99%

See 1 more Smart Citation

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Swami

Sharma²

2022

Silicon

View full text Add to dashboard Cite

show abstract

“…Binary and ternary logic D flip flop designs, shift registers and counters have been discussed and optimized in various published literature [15,18,26,27]. Senseamplifier based flip-flop (SAFF) with transistor count of 18 reduces clock swing as shown in Fig.…”

Section: Sense Amplifier Flip Flop (Saff)mentioning

confidence: 99%

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Swami¹,

Sharma²

2021

Preprint

View full text Add to dashboard Cite

Energy conservation and delay minimization are the two major goals while designing ultra-low-power digital integrated circuits at lower technology nodes. Here, silicon based carbon nanotube field effect transistor (CNTFET) has been explored as a novel material for future electronics design applications (EDA). In this paper, two energy-efficient switching activity minimization techniques have been applied with proposed designs. First technique detects the completion of sensing stage operation known as transition completion detection (TCD) technique. TC signal generated from NAND operation of complementary outputs of sensing stage which minimizes glitches in the complementary outputs of the latch stage. Another clock gating mechanism applied at the latch stage to smoothen the output waveforms Q and . The proposed and existing designs simulated using 32nm CMOS and 32nm CNTFET technology, indicating that the CNTFET based design reduces power by 45% and 36% respectively in comparison with conventional CMOS. Proposed Low Power Sense Amplifier Flip Flop with transition control detection (TCD-LPSAFF) and Ultra Low Energy Sense Amplifier Flip Flop (ULESAFF) give optimum power delay product (PDP) which is 35.7x10-18 J and 29.6x10-18 J respectively. Also, the effect of process variation has been analyzed at specified corners (FF, TT and SS) in the temperature range of -40º C to 120º C. The performance of all designs has been validated by functionality testing with variation in diameter, number of tubes and pitch respectively.

show abstract

“…Conventional TGFF is a well-known FF topology that is used in many earlier microprocessors and it is a modified version of the popular FF used in the PowerPC 603 processor (NXP Semiconductors, Eindhoven, Netherlands) [29][30][31]. Figure 1a shows the circuit diagram of TGFF, which consists of a master latch that captures the input D signal when the CLK is low and keeps it when the CLK is high; and a slave latch that operates on the opposite CLK levels as the signal is passed from master latch to slave latch while the CLK is high, and it is kept as long as the CLK is low.…”

Section: Conventional Transmission Gate Flip-flop (Tgff)mentioning

confidence: 99%

Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Hamed

Lee

2021

Electronics

View full text Add to dashboard Cite

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

show abstract

Flip-Flop Design in Nanometer CMOS

Cited by 14 publications

References 118 publications

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Contact Info

Product

Resources

About