Optical Buffering for Chip Multiprocessors: A 16GHz Optical Cache Memory Architecture

Maniotis, Pavlos; Fitsios, D.; Kanellos, George T.; Pleros, Nikos

doi:10.1109/jlt.2013.2290741

Cited by 41 publications

(26 citation statements)

References 45 publications

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“…These have both been experimentally shown to support speeds beyond 10 Gb/s, while in-depth frequency theoretical memory speed analyses [42,43] and validated time-domain SOA-based memory simulations [43,44] have revealed potential rates of up to 40 Gb/s. Furthermore, by combining optical Column/Row Address Selectors [45,46] and optical Tag Comparators [47], the first designs of a complete optical cache memory architecture for high-performance computers revealed a 16 GHz operation via physical layer simulations [48]. All of these have increased the maturity of optical memories towards penetrating the computing domain, where the use of electronics is so far undisputable, whereas in optical networks, optical FFs have been suggested for contention resolution [49].…”

Section: Introductionmentioning

confidence: 99%

Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations

et al. 2017

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Electronic Content Addressable Memories (CAM) implement Address Look-Up (AL) table functionalities of network routers; however, they typically operate in the MHz regime, turning AL into a critical network bottleneck. In this communication, we demonstrate the first steps towards developing optical CAM alternatives to enable a re-engineering of AL memories. Firstly, we report on the photonic integration of Semiconductor Optical Amplifier-Mach Zehnder Interferometer (SOA-MZI)-based optical Flip-Flop and Random Access Memories on a monolithic InP platform, capable of storing the binary prefix-address data-bits and the outgoing port information for next hop routing, respectively. Subsequently the first optical Binary CAM cell (B-CAM) is experimentally demonstrated, comprising an InP Flip-Flop and a SOA-MZI Exclusive OR (XOR) gate for fast search operations through an XOR-based bit comparison, yielding an error-free 10 Gb/s operation. This is later extended via physical layer simulations in an optical Ternary-CAM (T-CAM) cell and a 4-bit Matchline (ML) configuration, supporting a third state of the "logical X" value towards wildcard bits of network subnet masks. The proposed functional CAM and Random Access Memories (RAM) sub-circuits may facilitate light-based Address Look-Up tables supporting search operations at 10 Gb/s and beyond, paving the way towards minimizing the disparity with the frantic optical transmission linerates, and fast re-configurability through multiple simultaneous Wavelength Division Multiplexed (WDM) memory access requests.

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Section: Introductionmentioning

confidence: 99%

Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations

et al. 2017

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“…Moreover, recent work on demonstrating the most critical building blocks as integrated subsystems onto the silicon photonics fabrication platform [9] renders this scheme as highly promising for allowing the deployment of complete optical cache modules as silicon chips. Taking advantage of all these advances, we recently presented a complete and fully functional optical cache memory architecture that performs read/write operations directly in the optical domain [10], [11]. In this work, we proposed an all-optical cache memory that combines all the optical subsystems, such as read/write selection modules, row and column decoders, 2D RAM banks and tag comparison circuits.…”

Section: Introductionmentioning

confidence: 99%

“…In this work, we proposed an all-optical cache memory that combines all the optical subsystems, such as read/write selection modules, row and column decoders, 2D RAM banks and tag comparison circuits. Physical layer simulation scenarios carried out with the VPI Photonics simulation suite indicate error-free operation at speeds up to 16 GHz for both direct [10] and 2-way associative [11] mapping schemes.…”

Section: Introductionmentioning

confidence: 99%

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High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures

Maniotis

Gitzenis

Pleros

2015

2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing

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We present an optical bus-based Chip Multiprocessor architecture where the processing cores share an optical single-level cache unit. Physically, the optical cache is implemented externally in a separate chip located next to the CPU die. The cache interconnection system is realized through WDM optical interfaces that connect the shared cache module with the processing cores and the Main Memory via spatialmultiplexed optical waveguides; hence, the CPU-DRAM communication completely takes place in the optical domain. To evaluate the shared optical cache approach, we carry out systemlevel simulations of 6 realistic processor parallel workloads via the Gem5 platform. The optical cache architecture is compared against the conventional electronic Chip Multiprocessor topology that uses dedicated on-chip L1 electronic caches and a shared L2 cache. The results show significant reduction in the L1 miss rate of up to 96% for certain cases; on average, a performance speedup of up to 20.53% or a reduction of up to 65.8% in cache capacity requirements is attained. Combined with highbandwidth CPU-DRAM bus solutions based on optical interconnects, the proposed design is a quite promising system architecture that bridges the gap between high-speed optically connected CPU-DRAM schemes and high-speed optical memory technologies.

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“…Semiconductor optical amplifiers (SOAs) are already a well-established solution in the cost-and energy-critical domain of optical access networks, performing in a variety of optical functionalities; optical amplification offered by SOAs integrated with Electro-absorption Modulators [1], [2] or colorless reflective modulation provided by Reflective Semiconductor Optical Amplifiers (RSOAs) [3], [4] are just some indicative examples, with energy consumption being in both cases a vital parameter. Moreover, SOAs have been shown to enable advanced functionalities like optical random access memory (RAM) [5], [6], optical cache [7] and memory peripherals [8] and also in the area of chip-scale circuitry for DataCom and ComputerCom applications, where high-integration densities are expected to significantly increase operational temperatures, affecting the circuit's operation besides requiring power-hungry external cooling.…”

Section: Introductionmentioning

confidence: 99%

High gain 1.3-μm GaInNAs SOA with fast gain dynamics and enhanced temperature stability

et al. 2014

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Semiconductor optical amplifiers (SOAs) are a well-established solution of optical access networks. They could prove an enabling technology for DataCom by offering extended range of active optical functionalities. However, in such costand energy-critical applications, high-integration densities increase the operational temperatures and require powerhungry external cooling. Taking a step further towards improving the cost and energy effectiveness of active optical components, we report on the development of a GaInNAs/GaAs (dilute nitride) SOA operating at 1.3μm that exhibits a gain value of 28 dB and combined with excellent temperature stability owing to the large conduction band offset between GaInNAs quantum well and GaAs barrier. Moreover, the characterization results reveal almost no gain variation around the 1320 nm region for a temperature range from 20 o to 50 o C. The gain recovery time attained values as short as 100 ps, allowing implementation of various signal processing functionalities at 10 Gb/s. The combined parameters are very attractive for application in photonic integrated circuits requiring uncooled operation and thus minimizing power consumption. Moreover, as a result of the insensitivity to heating issues, a higher number of active elements can be integrated on chip-scale circuitry, allowing for higher integration densities and more complex optical on-chip functions. Such component could prove essential for next generation DataCom networks.

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Optical Buffering for Chip Multiprocessors: A 16GHz Optical Cache Memory Architecture

Cited by 41 publications

References 45 publications

Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations

Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations

High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures

High gain 1.3-μm GaInNAs SOA with fast gain dynamics and enhanced temperature stability

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