We report on the development of a flexible 2D optical fiber-based pressure sensing surface suitable for biomedical applications. The sensor comprises of highly-sensitive Fiber Bragg Grating elements embedded in a thin polymer sheet to form a 2x2 cm(2) sensing pad with a minimal thickness of 2.5mm, while it is easily expandable in order to be used as a building block for larger surface sensors. The fabricated pad sensor was combined with a low physical dimension commercially available interrogation unit to enhance the portability features of the complete sensing system. Sensor mechanical properties allow for matching human skin behavior, while its operational performance exhibited a maximum fractional pressure sensitivity of 12 MPa(-1) with a spatial resolution of 1x1cm(2) and demonstrated no hysteresis and real time operation. These attractive operational and mechanical properties meet the requirements of various biomedical applications with respect to human skin pressure measurements, including amputee sockets, shoe sensors, wearable sensors, wheelchair seating-system sensors, hospital-bed monitoring sensors.
The remarkable achievements in the area of integrated optical memories and optical random access memories (RAMs) together with the rapid adoption of optical interconnects in the Datacom and Computercom industries introduce a new perspective for information storage directly in the optical domain, enabling fast access times, increased bandwidth and transparent cooperation with optical interconnect lines. This article reviews state-of-the-art integrated optical memory technologies and optical RAM cell demonstrations describing the physical mechanisms of several key devices along with their performance metrics in terms of their energy, speed and footprint. Novel applications are outlined, concluding with the scaling challenges to be addressed toward allowing light to serve as both a data-carrying and data-storage medium.
In this paper, we demonstrate a novel RAM cell based only on three traveling waveguide semiconductor optical amplifier-cross gain modulation (SOA-XGM) switches. The RAM cell features wavelength diversity in the incoming bit signals and provides Read/Write operation capability with true random access exclusively in the optical domain. Two of the SOA-XGM switches are coupled together through an 70/30 coupler to form an asynchronous flip-flop, which serves as the memory unit. Random access to the memory unit is granted by a third SOA-ON/OFF switch and all three SOAs together form the proposed RAM cell. Proof-of-principle operation is experimentally demonstrated at 8 Mb/s using commercial fiber-pigtailed components. The distinctive simplicity of the proposed RAM cell architecture suggests reduced footprint. The proposed flip-flop layout holds all the credentials for reaching multi-Gb/s operational speeds, if photonic integration technologies are employed to obtain wavelength-scale waveguides and ultrashort coupling lengths. This is numerically confirmed for 10 Gb/s using a simulation model based on the transfer matrix method and a wideband steady-state material gain coefficient. Index Terms-Optical flip-flop, optical memory, optical signal processing, semiconductor optical amplifier (SOA), transfer matrix method (TMM).
We experimentally demonstrate an all-optical static random access memory (RAM) cell using a novel monolithic InP set-reset flip-flop (FF) chip and a single hybridly integrated semiconductor optical amplifier-Mach-Zehnder interferometer (SOA-MZI)-based access gate employing wavelength division multiplexing (WDM) data encoding. The FF device is a 6×2 mm2 InP chip having a 97.8% reduced footprint compared with previous FF devices that were successfully employed in optical RAM setups. Successful and error-free RAM operation is demonstrated at 5 Gb/s for both read and write functionalities, having a power penalty of 4.6 dB for write and 0.5 dB for read operations. The theoretical potential of this memory architecture to allow RAM operation with memory speeds well beyond 40 GHz, in combination with continuously footprint-reducing techniques, could presumably lead to future high-speed all-optical RAM implementations that could potentially alleviate electronic memory bottlenecks and boost computer performance
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1932-4537 (c)Abstract-Datacenter (DC) design has been moved towards the edge computing paradigm motivated by the need of bringing cloud resources closer to end users. However, the Software Defined Networking (SDN) architecture offers no clue to the design of Micro Datacenters (MDC) for meeting complex and stringent requirements from next generation 5G networks. This is because canonical SDN lacks a clear distinction between functional network parts, such as core and edge elements. Besides, there is no decoupling between the routing and the network policy. In this paper, we introduce Residue Defined Networking Architecture (RDNA) as a new approach for enabling key features like ultra-reliable and low-latency communication in MDC networks. RDNA explores the programmability of Residues Number System (RNS) as a fundamental concept to define a minimalist forwarding model for core nodes. Instead of forwarding packets based on classical table lookup operations, core nodes are tableless switches that forward packets using merely remainder of the division (modulo) operations. By solving a residue congruence system representing a network topology, we found out the algorithms and their mathematical properties to design RDNA's routing system that (i) supports unicast and multicast communication, (ii) provides resilient routes with protection for the entire route, and (iii) is scalable for 2-tier Clos topologies. Experimental implementations on Mininet and NetFPGA SUME show that RDNA achieves 600 ns switching latency per hop with virtually no jitter at core nodes and submillisecond failure recovery time.
We report an 8 × 8 silicon photonic integrated Arrayed Waveguide Grating Router (AWGR) targeted for WDM routing applications in O-band. The AWGR was designed for cyclic-frequency operation with a channel spacing of 10 nm. The fabricated AWGR exhibits a compact footprint of 700 × 270 μm. Static device characterization revealed 3.545 dB maximum channel loss non-uniformity with 2.5 dB best-case channel insertion losses and 11 dB channel crosstalk, in good agreement with the simulated results. Successful data routing operation is demonstrated with 25 Gb/s signals for all 8 × 8 AWGR port combinations with a maximum power penalty of 2.45 dB.
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