High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures

Abstract

We present an optical bus-based Chip Multiprocessor architecture where the processing cores share an optical single-level cache unit. Physically, the optical cache is implemented externally in a separate chip located next to the CPU die. The cache interconnection system is realized through WDM optical interfaces that connect the shared cache module with the processing cores and the Main Memory via spatialmultiplexed optical waveguides; hence, the CPU-DRAM communication completely takes place in the optical domain. To evaluate the shared optical cache approach, we carry out systemlevel simulations of 6 realistic processor parallel workloads via the Gem5 platform. The optical cache architecture is compared against the conventional electronic Chip Multiprocessor topology that uses dedicated on-chip L1 electronic caches and a shared L2 cache. The results show significant reduction in the L1 miss rate of up to 96% for certain cases; on average, a performance speedup of up to 20.53% or a reduction of up to 65.8% in cache capacity requirements is attained. Combined with highbandwidth CPU-DRAM bus solutions based on optical interconnects, the proposed design is a quite promising system architecture that bridges the gap between high-speed optically connected CPU-DRAM schemes and high-speed optical memory technologies.

A Survey of Novel Cache Hierarchy Designs for High Workloads

“…The conventional ways of implementing a higher level of cache hierarchies not only increases the total area of the chip and the energy consumption but also the miss rates with more number of cores and higher cache size. P. Maniotis et al [3] proposed a solution to the above problem by presenting an optical cache memory architecture that uses optical CPU-MM buses, in place of standard electronic buses, for connecting all optical subsystems. In contrast to the standard way of putting the L1 and L2 cache along with the core in order to match their speeds, the optical caches are kept on a separate chip, as shown in fig.…”

“…5. Performance graph for Solution 3 [3] or for bigger workloads which fit in the conventional LLC space.…”

“…This survey will look into three different perspectives, offered by three different studies [1] [2] [3], in tackling this issue. One solution suggests a new algorithm in servicing cache requests, one examines different sizes of the physical architecture of the hardware, while one investigates an optical bus-based architecture.…”

Optics in Computing: From Photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated Architectures

“…However, the recent advances on the still new technology of Optical Static RAMs and the first designs of optical cache memories [154]- [168] might allow an alternative visionary route towards an expanded disintegrated compute architecture with off-die shared optical caching [74]. This is illustrated in Fig.…”