On the Origins, Status, and Future of Flip Chip &amp; Wafer Level Packaging

Huffman, Alan; Garrou, P.

doi:10.4071/isom-2010-tp5-paper1

Cited by 5 publications

(4 citation statements)

References 20 publications

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“…The wafer-level packaging metallization approach is based on the use of spin-on dielectrics (e.g. polyimide) that inherently planarize topographies on the order of a few µm (typical routing layer thickness) [3]. This property eliminates the need for CMP, providing some cost reduction in processing.…”

Section: Multi-level Metallization Process Modulesmentioning

confidence: 99%

“…The order in which these modules are integrated and the materials set used for the MLM depends on the Si interposer design requirements and application. Specifically, the line/space density requirement of the metal routing layers will dictate whether a dual damascene MLM approach (higher line density and cost of fabrication) or wafer-level packaging MLM approach (lower line density and cost of fabrication) is needed [2,3]. Similarly, the size and density of TSVs in the interposer will determine whether a full thickness or thinned Si interposer is required, as well as when (vias-first or viaslast) and what type of TSV is formed (filled or un-filled).…”

Section: Introductionmentioning

confidence: 99%

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Process integration and testing of TSV Si interposers for 3D integration applications

Lannon

Hilton

Huffman

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Two 3D Si interposer demonstration vehicles containing through-Si vias (TSVs) were successfully fabricated using integration of two different TSV formation and multilevel metallization (MLM) process modules.The first Si interposer vehicles were made with a dual damascene frontside MLM (5 levels), backside TSV (unfilled, vias-last), and backside metallization (2 levels) process sequence on standard thickness 6" wafers. The front-side MLM was comprised of 4 metal routing layers (2 µm Cu with 2 µm oxide interlayer dielectric) and 1 metal pad layer. Electrical yield as high as 100% was obtained on contact chain test structures containing 26,400 vias between the front-side MLM layers, while the average contact resistance between the dual damascene levels was < 4 mΩ per via. TSV dimensions of 100 and 80 µm diameter and 6:1 aspect ratio were investigated. DRIE bottom clear process conditions were optimized for each via dimension to produce 100% yield on TSV contact chains with up to 540 vias. The optimized DRIE conditions also resulted in TSV resistance below 30 mΩ and sufficient TSV isolation resistance (>100MΩ/via at 3.3V) for the target application. Functional testing of two die (4 cm x 3.7 cm die size) showed that 99% of the functional circuit path nets had acceptable continuity and isolation. The second Si interposer vehicles were fabricated using a vias-first TSV (filled, blind vias), waferlevel packaging (WLP) front-side MLM (2 levels), wafer thinning (via reveal), and WLP-MLM (1 level) process sequence on stock 6" wafers. Via dimensions for the viasfirst interposers were 50 µm diameter x 315 µm depth or 80 µm diameter x 315 µm depth (6:1 or 4:1 aspect ratios). The front and backside MLM was formed with a 2 µm Cu routing layer and one of two spin-on dielectrics (polyimide or ALX) for evaluation of polymer dielectric process compatibility with Cu-filled TSVs and thinned wafer processing. Details of the process modules and process integration required to realize the TSV Si interposers are described.

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Section: Multi-level Metallization Process Modulesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Process integration and testing of TSV Si interposers for 3D integration applications

Lannon

Hilton

Huffman

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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show abstract

“…The MLM L/S density design requirements dictate whether a fabrication process based on damascene Cu embedded in SiO 2 (providing a higher line density) or electroplated Cu and spin-on dielectrics (providing a lower line density and typically lower cost of fabrication) is needed [2], [3]. Similarly, the interposer thickness is driven by the required TSV dimensions, cost of fabrication, and requirements for mechanical, thermal, and electrical performance needed for the specific application.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Testing of a TSV-Enabled Si Interposer With Cu- and Polymer-Based Multilevel Metallization

Lannon

Hilton

Huffman

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

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An electrically functional freestanding Si interposer for 3-D heterogeneous integration applications is designed and successfully fabricated. The interposer employs multilevel metallization (MLM) on the frontside of the wafer and Cu-filled through-Si vias (TSVs) and MLM on the backside. The MLM structures use electroplated Cu and polymer dielectrics of the type used in wafer-level packaging. The fabrication flow of the 3-D interposer test vehicle incorporates the formation of TSVs, the deposition and patterning of two routing levels of frontside MLM, wafer thinning, and the deposition and patterning of backside MLM. TSVs 80 µm in diameter, 315 µm in depth, and 80 µm in diameter, 265-µm depth (4:1 or 3:1 aspect ratio, respectively) are demonstrated. The frontside and backside MLM were formed with 3-µm-thick Cu routing layers and 5-µm-thick spin-on dielectric layers. Daisy chains consisting of 528 TSVs connecting the frontside and backside metal layers are tested for electrical continuity. Individual TSV operability exceeds 99.98%. Details of the MLM and TSV process modules, including thermal stabilization of Cu-filled TSVs and process integration required to successfully obtain the high TSV operability, are described. Index Terms-Multilevel metallization (MLM), Si interposer, through-Si vias (TSVs).

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“…WL-CSP is attractive due to it cost per units, elimination of substrate and process simplification. Different type of technologies had been reviewed such as initial redistribution process by Fujitsu, Oki, FCT, Unitive and IZM-Berlin [1][2][3][4]. Tessera and Amkor technologies attach a film to the wafer to create rerouting.…”

Section: Introduction 11 Chip Scale Packaging Challengesmentioning

confidence: 99%

A Review of Moldflow and Finite Element Analysis Simulation of Chip Scale Packaging (CSP) for Light Emitting Diode (LED)

Ching

Abdullah

2022

ARFMTS

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LED technology has been evolving aggressively in recent years from incandescent bulb during older days to as small as chip scale package. There is tremendous pressure to stay competitive in the market by optimizing products to next level of performance and reliability with shortest time to market. This changes the conventional way of product design and development to virtual prototyping by means of Computer Aided Engineering (CAE). The objective of the paper is to review challenges in chip scale packaging application in LED technology. The first part of the paper covered the literature survey of Chip Scale Packaging (CSP) in Light Emitting Diodes (LED), CSP architecture challenges, molding process and material for CSP. The findings of literature found that very few researchers had study silicone encapsulations process in CSP for LED in term of material characterization, mold process and simulation. Findings also shows that deployment Computational Fluid Dynamic (CFD) and integration of virtual prototyping using Finite Element Analysis (FEA) in product development in CSP for semiconductor industry had greatly reduced the time to market. However, there are very few papers discuss the application for CSP technology in LED industry. Second objective of the papers is discussion of methodolology in molding material characterization and simulation methodology. CFD helps to simulate the flow pattern of molding material as a function of different temperature, molding parameters settings for voids and displacement. FEA also help to evaluate the deformation of silicone in panel form and enable designer to predict the displacement of devices with different silicone.

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On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging

Cited by 5 publications

References 20 publications

Process integration and testing of TSV Si interposers for 3D integration applications

Process integration and testing of TSV Si interposers for 3D integration applications

Fabrication and Testing of a TSV-Enabled Si Interposer With Cu- and Polymer-Based Multilevel Metallization

A Review of Moldflow and Finite Element Analysis Simulation of Chip Scale Packaging (CSP) for Light Emitting Diode (LED)

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