On the efficacy of write-assist techniques in low voltage nanoscale SRAMs

Abstract

Read and write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. In this paper, we review the efficacy of four leading write-assist (WA) techniques and their behavior at lower supply voltages in commercial SRAMs from 65nm, 45nm and 32nm low power technology nodes. In particular, the word-line boosting and negative bit-line WA techniques seem most promising at lower voltages. These two techniques help reduce the value of W Lcrit by a factor of ∼2.5X at 0.7V and also decrease the 3σ spread by ∼3.3X, thus significantly reducing the impact of process variations. These write-assist techniques also impact the dynamic read noise margin (DRNM) of half-selected cells during the write operation. The negative bit-line WA technique has virtually no impact on the DRNM but all other WA techniques degrade the DRNM by 10-15%. In conjunction with the benefit (decrease in W Lcrit) and the negative impact (decrease in DRNM), overhead of implementation in terms of area and performance must be analyzed to choose the best write-assist technique for lowering the SRAM Vmin.

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

“…Transient simulations are required to quantify the effect of implementation details that have a large effect on failure rates, such as the shape of the boosted wordline waveform. Other works have resolved this problem by investigating the impact of assist techniques on dynamic writeability by assuming that failure metrics can be fit to a particular distribution [3]. Accelerated Monte Carlo techniques such as importance sampling (IS) do not make any assumptions about failure distributions and can track SRAM tail cells [4].…”

Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies

“…We can see that the signals are opposite with respect to those of a regular SRAM cell, thus, any strategy to improve SRAM speed or reliability [12] will also be applicable to the complementary cell design, including V dd tuning, word-line boosting (the same effect will be obtained driving the word-line below zero during read and write), or negative bit-line voltages (the equivalent for CSRAM consists on driving the selected bit-line above the nominal supply voltage during write). In the case of an 8T SRAM cell, the write process is the same.…”

Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing

“…Apart from body-biasing, sourcebias has been also investigated for variability mitigation. Together with other voltage tuning methods, the source-biasing is included in the family of circuit assist techniques [16]- [18]. This paper focuses on the analysis of permanent faults in SRAM arrays that are caused by resistive-open defects in the core cell.…”