SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Zimmer, Brian; Toh, Seng Oon; Vo, Huy T.; Lee, Yunsup; Thomas, Olivier; Asanović, Krste; Nikolić, Borivoje

doi:10.1109/tcsii.2012.2231015

Cited by 63 publications

(22 citation statements)

References 14 publications

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“…We can improve the read margin by using one of the below mentioned read assist circuit techniques [4].…”

Section: Circuit Techniquesmentioning

confidence: 99%

Improvement of SRAM stability using read and write assist techniques

Sreenivasulu

R³

2017

IJET

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The objective of this paper is to demonstrate how to improve the read stability of the SRAM cell using the read assist technique. SRAM cell stability is the primary concern for the present and future technologies due to process variations like Vt and Vdd scaling, etc. So it requires additional circuit techniques such as write and read to assist to improve the stability of SRAM memories. To accomplish the non-destructive read operation, we need to either weaken the pass transistor or strengthen the pull-up transistor during the read operation. Towards decrease of pass transistor strength, we implemented the lower word line voltage as read assist circuit. The lower word line voltage will help the selected and un-selected columns (for higher column mux options) during a read operation. But during write operation the lowered word line voltage scheme will impact the write operation. So, in order to improve the read margin we used read assist technique at the same time to ensure that write operation is successful we combined the negative bit line write assist scheme along with read assist technique. The proposed assist circuit gain the power and read margin improvement of 10%, 30% respectively. We observed the read margin analysis at process, voltage and temperature corners.

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“…We can improve the read margin by using one of the below mentioned read assist circuit techniques [4].…”

Section: Circuit Techniquesmentioning

confidence: 99%

Improvement of SRAM stability using read and write assist techniques

Sreenivasulu

R³

2017

IJET

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“…In this work, NBL technique is being used as write assist scheme, since this is the most effective technique to reduce the SRAM V MIN [16]. Also, this technique shows highest WM without reducing the ADM of the half selected bitcells [2].…”

Section: Proposed Reduced Coupling Signalmentioning

confidence: 99%

A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques

Kumar¹,

Saha²,

Gupta³

2017

RADIOENGINEERING

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“…While reduced voltage does not present challenges to the logic gates, SRAM circuits begin to fail as voltage drops [30]. We see two promising approaches to enable voltage scaling of on-chip RAM arrays.…”

Section: Reduced-voltage Operationmentioning

confidence: 99%

Scaling the Power Wall: A Path to Exascale

Villa

Johnson

O'Connor³

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

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Abstract-Modern scientific discovery is driven by an insatiable demand for computing performance. The HPC community is targeting development of supercomputers able to sustain 1 ExaFlops by the year 2020 and power consumption is the primary obstacle to achieving this goal. A combination of architectural improvements, circuit design, and manufacturing technologies must provide over a 20× improvement in energy efficiency. In this paper, we present some of the progress NVIDIA Research is making toward the design of Exascale systems by tailoring features to address the scaling challenges of performance and energy efficiency. We evaluate several architectural concepts for a set of HPC applications demonstrating expected energy efficiency improvements resulting from circuit and packaging innovations such as low-voltage SRAM, low-energy signaling, and on-package memory. Finally, we discuss the scaling of these features with respect to future process technologies and provide power and performance projections for our Exascale research architecture.

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SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Cited by 63 publications

References 14 publications

Improvement of SRAM stability using read and write assist techniques

Improvement of SRAM stability using read and write assist techniques

A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques

Scaling the Power Wall: A Path to Exascale

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