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Abstract-Optimization of SRAM yield using dynamic stability metrics has been evaluated in the past to ensure continued scaling of bitcell size and supply voltage in future technology nodes. Various dynamic stability metrics have been proposed but they have not been used in practical failure analysis and compared with conventional static margins. This work compares static and dynamic metrics to identify expected correlations. A dynamic stability characterization architecture using pulsed word-lines is implemented in 45 nm CMOS to identify sources of variability, and their impact on SRAM stability. Static read margins were observed to overestimate failures by 10-100 X while static write margins failed to predict outliers in critical writeability. Critical writeability was demonstrated to exhibit an enhanced sensitivity to process variations, random telegraph noise (RTN), and negative bias temperature instability (NBTI), compared to static write margins.

Abstract-Random telegraph signal (RTS) is shown to be an intrinsic component of the shift in MOSFET threshold voltage (V th ) due to bias temperature instability (BTI). This is done by starting from a well-known model for negative BTI (NBTI), to derive the formula for RTS-induced V th shift. Based on this analysis, RTS simply contributes an offset in NBTI degradation, with an acceleration factor that is dependent on the gate voltage and temperature. This is verified by 3-dimensional (3-D) device simulations and measurements of 45nm-node bulk-Si PMOS transistors. It has an important implication for design of robust SRAM arrays in the future: design margin for RTS should not be simply added, because it is already partially accounted for within the design margin for NBTI degradation.

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A method for characterizing dynamic SRAM stability using pulsed wordlines, is demonstrated in 45nm CMOS. Static read margins were observed to overestimate failures by up to 1000x while static write margins failed to predict outliers in dynamic write stability. Dynamic write stability was demonstrated to exhibit an enhanced sensitivity to process variations, and negative bias temperature instability (NBTI), compared to static write margins. Introduction Static (DC) noise margins are often used to characterize SRAM because of their simple interpretation and measurements, although they overestimate read failures and underestimate write failures. Alternately, dynamic SRAM stability has been proposed to be characterized by using critical wordline pulse width, which produces better estimates of failure rates [1][2][3], but this method has not been compared with static margins. This work demonstrates the on-chip circuitry for characterizing dynamic SRAM stability using wordline pulses with accuracy better than 10ps. Fig. 1 shows the SRAM array configuration for the characterization of the dynamic metrics and the necessary infrastructure for collecting static metrics for the purpose of establishing correlations between the measured results. A pulse of programmable width is generated centrally and delivered to a wordline following the row decoders. To avoid process-and layout-induced uncertainties, the exact pulse width is measured by wordline samplers located on every wordline. Each sampler consists of a high bandwidth dual-phase-clocked track-and-hold circuit followed by a comparator with offset calibration. The use of dual-phase-clocked track-and-hold circuits as well as calibration of the phase of these dual-phase clocks is essential for sampling the fast rising and falling transitions of wordline pulses with minimal distortion. This calibration scheme produces finer resolution compared to delay-line based schemes [4]. All array bitlines are accessible externally through a bitline switch network using 4-terminal Kelvin sensing to bias the bitline voltages during dynamic stability measurements as well as to characterize static read and write SRAM metrics [5]. Fig. 2 illustrates key circuit blocks for enabling accurate on-chip pulse generation. Two clock signals with a slight difference in clock period (ΔT) are used to produce a pulse train with a pulse width difference of ΔT between successive pulses. A counter is then used to select the desired pulse, based on a programmed digital codeword. This counter is synchronized by a sync signal which is asserted when Φ 0 and Φ 1 have the desired phase relationship. Phase calibration of the sampling edges of the wordline samplers is accomplished by capacitively summing both sampling edges and adjusting the skew between them to reduce the glitch on the summing node. A Monte Carlo simulation of this scheme reveals that it reduces the phase offset of respective edges to less than 3 ps. The impact of clock jitter on measurement accuracy is reduced through averaging. The b...