Analysis of the relationship between random telegraph signal and negative bias temperature instability

Abstract

Abstract-Random telegraph signal (RTS) is shown to be an intrinsic component of the shift in MOSFET threshold voltage (V th ) due to bias temperature instability (BTI). This is done by starting from a well-known model for negative BTI (NBTI), to derive the formula for RTS-induced V th shift. Based on this analysis, RTS simply contributes an offset in NBTI degradation, with an acceleration factor that is dependent on the gate voltage and temperature. This is verified by 3-dimensional (3-D) device simulations and measurements of 45nm-node bulk-Si PMOS transistors. It has an important implication for design of robust SRAM arrays in the future: design margin for RTS should not be simply added, because it is already partially accounted for within the design margin for NBTI degradation.

Accurate Prediction of Random Telegraph Noise Effects in SRAMs and DRAMs

“…This enabled us to generate SRAM/DRAM failures within relatively short simulation runs that could be visually depicted in this paper. Also, the shortened time constants illustrate SAMURAI/MUSTARD's ability to perform accelerated RTN testing, a much needed feature [1], [4]. The motivation is that, if traps transition only once every millisecond or so, it would take prohibitively long measurements or simulations to produce statistical failure estimates for circuits clocked in the nanosecond range, like SRAMs.…”

“…Measurement-based characterizations: These involve subjecting post-fabrication SRAM/DRAM arrays to a large number of measurement tests, in the hope of detecting vulnerabilities to RTN [1]. This is the primary mode of RTN analysis available today for SRAMs and DRAMs.…”

“…Moreover, unlike other sources of variability, RTN is a temporal effect that cannot be completely characterized by measurement data alone. For example, identical tests carried out on the same SRAM/DRAM chip at different times can yield completely different success or failure outcomes [1]. Thus, even if a large number of measurements indicate that a chip is robust to RTN, it may in fact not be so.…”

“…At the 22-nm node, RTN (coming on top of parameter variability) is large enough to push the stacked bar above the minimum supply voltage, thereby driving design margins negative. In fact, RTN-induced SRAM failures, leading to transient read or write bit errors, have already been experimentally reported [1], [4].…”

Technology variability from a design perspective

“…This is due to the fact that when convolving a longtailed distribution (RTS) with a normal distribution (RDF), the outliers in the long-tailed distribution have a low probability of being the most probable failure point in the design [44]. Furthermore, both theoretical and experimental analyses suggest that at least some components of RTS noise and BTI stem from the same traps, and therefore should be included in the same margin [51].…”