Variability in Nanometer Technologies and Impact on SRAM

Abu-Rahma, Mohamed H.; Anis, Mohab

doi:10.1007/978-1-4614-1749-1_2

Cited by 6 publications

(5 citation statements)

References 74 publications

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“…As Figure 1 shows, new technologies were introduced progressively with the newer smaller transistors [10]. Recent studies also verify that 22nm chips utilizing new tri-gate transistor technology further reduced leakage currents [7,11]. However, leakage currents and therefore static power remain to be almost as significant as the dynamic power [7,12].…”

Section: Chip Power Consumptionmentioning

confidence: 99%

Energy saving potential of low-temperature cooling of computers

Khalifa

Erden

Rougé

2014

Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)

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Current trends in data center cooling infrastructure design drive toward raising the coolant temperature to as high a level as equipment reliability allows in order to reduce the energy consumed by the cooling infrastructure and, consequently, improve (i.e., decrease) the power utilization effectiveness (PUE). However, as currently applied, PUE would appear to have deteriorated if measures are taken to reduce the energy consumption of the servers themselves. Because the temperature-dependent leakage power dissipation of modern deep-submicron computer chips constitutes a large fraction of the total power dissipation of these chips, the power consumption of such chips can be reduced by operating them at lower temperature. Not only does low-temperature operation reduce leakage power dissipation, but also it increases reliability and opens the potential for increasing the chip clock speed. However, these benefits may not lead to a reduction in the overall power consumption of the system of the servers and their associated cooling infrastructure if the leakage power reductions are more than offset by an increase in the power consumption of the low -temperature cooling infrastructure. In this paper we present a preliminary analytical study of a power and refrigeration cascade system (PARCS) that has the potential to realize the benefits of chip lowtemperature operation while decreasing the overall power consumption of the servers and their cooling infrastructure. We describe a parametric conceptual model of the combined servers and PARCS as a function of the coolant temperature and show that the optimum coolant temperature of servers equipped with 45, 32 and 22 nm chips could be substantially lower than the 27°C recommended by ASHRAE.

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Section: Chip Power Consumptionmentioning

confidence: 99%

Energy saving potential of low-temperature cooling of computers

Khalifa

Erden

Rougé

2014

Fourteenth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm)

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“…The tail of Vmin range distribution increases based on the number of observations (more measurements) or the amount of samples from multiple reads for the same memory bits. It is noted that Vt variation due to RTN has a non-Gaussian distribution with a long tail; therefore larger quantities of samples are required to quantify the RTN effect [9,10]. The aging data with multiple tests is shown in Fig.…”

Section: Vmin Aging and Rtnmentioning

confidence: 99%

Protecting against emerging vmin failures in advanced technology nodes

Lee

Haggag²,

Eklow

2014

2014 International Test Conference

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As technology and voltage scale, both intrinsic and extrinsic Vmin failures can occur at a significant rate. These failures can impact yield and reliability. We propose a novel guardband and advanced outlier limits (AOL) methodology to protect against intrinsic and extrinsic Vmin failures. This paper will demonstrate the impact of aging, RTN and HKMG process variation on Vmin. The data will be used to establish guardbands and AOL to minimize failures during testing and in the field. IntroductionTechnology advancements in Big Data and the data center are putting pressure on memory suppliers to deliver much more memory in smaller packages with lower power and higher reliability. In order to meet these requirements, memory suppliers are pushing the operating voltages closer and closer to Vmin (the minimum voltage level at which a part will reliably operate). The operating margins with respect to Vmin are therefore becoming tighter, and increasing the likelihood of failures. This increase in failure rate is in addition to the failures that naturally occur based on the sheer amount of memory in the data center.As a consequence of technology scaling, process variations, aging, RTN (Random Telegraph Noise), which increases device V t, has become a dominant mechanism degrading device maximum operating frequency (F max ) and minimum operating voltage (V min ). For a device with overdrive (V dd -V t ), an increase in V t requires an increase in minimum V dd to maintain same overdrive, hence V min shift is proportional to V t shift [1]. Vmin is a risk indicator that is based on potential conditions described above.Furthermore to enable higher performance at lower voltage and lower leakage levels, the transistor gate oxide has moved from silicon oxynitride / poly gate (SiON/Poly) to high-k / metal gate (HKMG) which further has reduced intrinsic reliability margin [2]; requiring more novel guard banding and screening techniques for reliability.Complicating matters even further, memory content has doubled for each technology generation which compounds the challenges faced by shrinking memory cells. In deeply scaled technologies, local Vt fluctuations, BTI and RTN are the three biggest issues [3] impacting the margin between the operating supply voltage (Vdd) and the minimum supply voltage below which an SRAM cell cannot be operated (Vmin). Scaling to 0.5X SRAM cell size constant Vmin becomes difficult. Since Vt cannot be scaled down aggressively, due to short channel effect, power-supply voltage (Vdd) has not been scaled down in proportion to the MOSFET channel length. This is especially true for SRAM due to shrinking headroom and rising Vmin. The impact of memory bit cell density and its Vmin trade-off is significant and the risk needs to be mitigated.There is plenty of published work which discusses the BTI impact on parametric or Vmin drift, including [4,5]. However, details regarding comprehensive protection against Vmin failures are very limited. In this paper, we present a methodology to analyze the various contributions...

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“…The NBTI ageing simulation has been conducted at circuit-level using a power-law model expressed by (1). The model has been implemented through a unified reliability interface on Cadence Relxpert simulator [29]…”

Section: Simulation Setup and Nbti Modelmentioning

confidence: 99%

“…This operating condition stands true for any SRAM cell as whatever the stored data; one of its PMOS will be undergoing an NBTI stress. Moreover, CMOS SRAM continues to be the technology of choice for cache memory despite the progressive introduction of new emerging memory technologies [1], As such, with technology scaling, NBTI will continue to be the main reliability challenge for current and future generation of SRAMs [3][4][5][6]. Thus, ageing-aware design techniques that alleviate NBTI have to be introduced to ensure reliable systems embedding them.…”

Section: Introductionmentioning

confidence: 99%

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Sizing of the CMOS 6T‐SRAM cell for NBTI ageing mitigation

Chenouf

Djezzar

Bentarzi

et al. 2020

IET Circuits, Devices & Systems

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This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T-SRAM cell could be properly sized for improved read stability and write-ability.

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Variability in Nanometer Technologies and Impact on SRAM

Cited by 6 publications

References 74 publications

Energy saving potential of low-temperature cooling of computers

Energy saving potential of low-temperature cooling of computers

Protecting against emerging vmin failures in advanced technology nodes

Sizing of the CMOS 6T‐SRAM cell for NBTI ageing mitigation

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