New method for parameter extraction in deep submicrometer MOSFETs

Mourrain, C.; Cretu, Bogdan; Ghibaudo, G.; Cottin, P.

doi:10.1109/icmts.2000.844428

Cited by 40 publications

(39 citation statements)

References 7 publications

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“…A lot of methods have been proposed for the MOSFET parameter extraction but they are generally restricted to the above threshold region and mostly assume that the inversion charge varies linearly with gate voltage overdrive [1][2][3][4][5][6][7][8][9][10][11]. As the supply voltage Vdd is reduced with device scaling, the operating gate bias moves closer to the threshold voltage (near threshold operation), and the assumption that the inversion charge varies approximately linearly with gate voltage overdrive becomes less and less accurate.…”

Section: Introductionmentioning

confidence: 98%

Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

Karatsori

Theodorou

Ioannidis

et al. 2015

Solid-State Electronics

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Section: Introductionmentioning

confidence: 98%

Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

Karatsori

Theodorou

Ioannidis

et al. 2015

Solid-State Electronics

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“…In order to investigate the hole transport behaviour in these devices, parameters extraction have been performed. We use an original strategy which combines the method based on the Id/ Gm function published by [9] and the Shift and Ratio technique. Electrical channel length, access resistance (Rsd) and mobility parameters (µ0, θ 1 and θ 2 ,equation presented in figure 10) have been extracted in the linear regime.…”

Section: Short Channel Transistor Behaviourmentioning

confidence: 99%

First ultra-thin film FDSOI devices with CMP-less TOtally SIlicided (TOSI) gate Integration

Fenouillet-Béranger

Gallon²,

Vandooren³

et al. 2006

2006 European Solid-State Device Research Conference

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In this paper we present a study of the integration of a TOSI gate process on fully-depleted SOI devices by using a CMP-less approach and a detailed electrical characterization of NMOS and PMOS transistors, including transport properties. Tuning of the workfunction has been observed for the NMOS devices by doping the polysilicon before gate silicidation. Functional PMOS and NMOS devices have been tested down to 50nm gate length. PMOS devices exhibits very good Ion/Ioff performances (Ion: 492µA/µm at Ioff: 25nA/µm @ Vdd -1.2V) despite the relatively thick gate oxide thickness used. The inverters' functionality of the FDSOI SRAM cell with a size of 0.99µm 2 has also been demonstrated, reflecting that this technology is a very promising candidate for 45nm LP node and beyond.

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“…In addition, it can be limited by the series resistance R sd (extrinsic property). In order to differentiate these effects, modelling of I d (V g ) characteristics using linear current parameter extraction [9] has been applied. In the drain current model used, the effective mobility is assumed to vary with the gate voltage V g according to:…”

Section: Parameter Extractionmentioning

confidence: 99%