Network flow based datapath bit slicing

Xiang, Hua; Cho, Minsik; Ren, Haoxing; Ziegler, Matthew M.; Puri, Ruchir

doi:10.1145/2451916.2451954

Cited by 13 publications

(5 citation statements)

References 13 publications

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“…However, in datapath logic designs, generally cells are characterized by a high degree of bit-wise parallelism that conventional placement has shown to be sub-optimal [37]. In designs where there are many embedded datapaths, extracting the datapaths and plac ing them with random logics appropriately has the potential to significant improve the overall StWL [38][39][40]. Fig.…”

Section: Datapath Placementmentioning

confidence: 99%

Machine learning and pattern matching in physical design

Pan

Matsunawa

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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A BSTRACTMachine learning (ML) and pattern matching (PM) are pow erful computer science techniques which can derive knowledge from big data, and provide prediction and matching. Since nanometer VLSI design and manufacturing have extremely high complexity and gigantic data, there has been a surge re cently in applying and adapting machine learning and pat tern matching techniques in VLSI physical design (including physical verification), e.g., lithography hotspot detection and data/pattern-driven physical design, as ML and PM can raise the level of abstraction from detailed physics-based simulations and provide reasonably good quality-of-result. In this paper, we will discuss key techniques and recent results of machine learning and pattern matching, with their applications in phys ical design.

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Section: Datapath Placementmentioning

confidence: 99%

Machine learning and pattern matching in physical design

Pan

Matsunawa

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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“…The Datapath Synthesis placement algorithm was added to the PDSrtl synthesis program to build upon designer supplied preplacement [10], [11]. Using preplaced cells and macro pins as anchors, this new placement algorithm infers structure in the macro and attempts to align datapath portions of the macro to the anchors, while non-datapath portions of the macro revert to convention placement algorithms more appropriate for "random logic".…”

Section: A Structured Synthesismentioning

confidence: 99%

“… 10. The macro optimization methodology is based on a tailored flow emphasizing parallel design space exploration.…”

mentioning

confidence: 99%

POWER8 design methodology innovations for improving productivity and reducing power

Ziegler

Puri

Philhower

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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The design complexity of modern high performance processors calls for innovative design methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets.This paper describes new design approaches employed by the POWER8 processor design team to address complexity and power consumption challenges. Improvements in productivity are attained by leveraging a new and more synthesis-centric design methodology. New optimization strategies for synthesized macros allow power reduction without sacrificing performance. These methodology innovations contributed to the industry leading performance of the POWER8 processor. Overall, POWER8 delivers a 2.5x increase in per-socket performance over its predecessor, POWER7+, while maintaining the same power dissipation.

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“…The Datapath Synthesis placement algorithm was added to the PDSrtl synthesis program to build upon designer supplied preplacement [32]. Using preplaced cells and macro pins as anchors, this new placement algorithm infers structure in the macro and attempts to align datapath portions of the macro to the anchors, while non-datapath portions of the macro revert to convention placement algorithms more appropriate for "random logic".…”

Section: Structured Synthesismentioning

confidence: 99%

Bridging high performance and low power in processor design

Puri

Choudhury

Qian

et al. 2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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The design complexity of modern high performance processors calls for innovative design techniques and methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets. This paper describes new processor design and optimization approaches that bridge the gap between high performance and low power. These techniques are flexible as they rely on automated synthesis-centric optimizations to enable power reduction without sacrificing performance. These methodology innovations contributed to the industry leading performance of the POWER8 processor.

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Network flow based datapath bit slicing

Cited by 13 publications

References 13 publications

Machine learning and pattern matching in physical design

Machine learning and pattern matching in physical design

POWER8 design methodology innovations for improving productivity and reducing power

Bridging high performance and low power in processor design

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