POWER8 design methodology innovations for improving productivity and reducing power

Abstract

The design complexity of modern high performance processors calls for innovative design methodologies for achieving time-to-market goals. New design techniques are also needed to curtail power increases that inherently arise from ever increasing performance targets.This paper describes new design approaches employed by the POWER8 processor design team to address complexity and power consumption challenges. Improvements in productivity are attained by leveraging a new and more synthesis-centric design methodology. New optimization strategies for synthesized macros allow power reduction without sacrificing performance. These methodology innovations contributed to the industry leading performance of the POWER8 processor. Overall, POWER8 delivers a 2.5x increase in per-socket performance over its predecessor, POWER7+, while maintaining the same power dissipation.

Toward metrics of design automation research impact

“…Fig. 15: Synthesized macro counts in IBM POWER processors [57]. Returning to the MPU model and roadmap in the ITRS System Drivers chapter, we see that the 1.4× per node frequency scaling predicted in 2001 was oblivious to platform power limits, which were added into the roadmap in 2007.…”

Progress in a novel architecture for high performance processing

“…The IBM POWER8 processor has 12 cores, 64K data cache and 32K instruction cache. [16][17][18][19][20] Four levels of caches are applied which include 512 KB SRAM L2, 96 MB eDRAM shared L3 and 128 MB eDRAM L4. Its memory ability can be up to 230 GB=s and it provides abundant bus interfaces.…”