Machine learning and pattern matching in physical design

Yu, Bei; Pan, David Z.; Matsunawa, Tetsuaki; Zeng, Xuan

doi:10.1109/aspdac.2015.7059020

Cited by 36 publications

(9 citation statements)

References 45 publications

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“…Then, the output of cell d1 is connected to cell e1, and the output of cell e1 is connected to cells f1 and e2. The output connection vectors of cell d1 with different distance values can be computed as given in (6)− (8). Their connection vectors can effectively express the connectivity information for both the direct (dist = 1) and indirect (dist > 1) connections:…”

Section: Connection Vector Computationmentioning

confidence: 99%

“…Due to their excellent performance, machine learning technologies have become prevalent in various industries. In terms of the physical design, supervised learning technologies are widely applied [8] in fields such as lithography hotspot detection [9, 10], lithography friendly routing [11], clock optimisation [12], and routability optimisation [13, 14]. In Fig.…”

Section: Introductionmentioning

confidence: 99%

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Effective datapath logic extraction techniques using connection vectors

Wang

Yeo

Shin

2019

IET Circuits, Devices & Systems

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Datapath macros are essential components of integrated circuits. The high regularity of datapaths allows compact layout design during placement. In some cases, datapath macros are manually pre-designed and pre-placed. However, datapath macros are frequently mixed with other circuits and they need to be extracted to capitalise on their regularity. In this study, the cells of a given circuit are accurately classified based on their size and pin information, and novel connection vectors to represent aspects of the connectivity among the cells have been proposed. By using the connection vectors of the cells, the similarity of connections is evaluated to extract potential datapath stages that constitute functional steps of a datapath. Two new efficient datapath logic extraction techniques (EDLETs) have been implemented based on the connection vectors for extracting potential datapaths in the circuit. One is the procedure-based method, and the other is the machine learning-based method. When compared with state-of-the-art methods, the experiments show that both the procedure-based and the learning-based methods proposed in this study efficiently extract potential datapaths from the Modified International Symposium on Physical Design (MISPD) 2011 Datapath Benchmark Suite. The extraction results of the proposed EDLET can be forwarded to a datapath placement tool for placing datapaths with a regular structure.

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Section: Connection Vector Computationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Effective datapath logic extraction techniques using connection vectors

Wang

Yeo

Shin

2019

IET Circuits, Devices & Systems

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“…Machine learning, as a powerful computer science technique, is capable of analyzing big data and providing prediction and matching. There have been some attempts applying machine learning to solve physical design problems such as lithography hotspot detection, datapath placement, and clock optimization [11] . Since physical design involves millions of units and is highly complex, machine learning haS gained more and more attention.…”

Section: Introductionmentioning

confidence: 99%

An accurate detailed routing routability prediction model in placement

Zhou

Wang

et al. 2015

2015 6th Asia Symposium on Quality Electronic Design (ASQED)

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Routability is one of the primary objectives in placement. There have been many researches on forecasting routing problems and improving routability in placement but no perfect solution is found. Most traditional routability-driven placers aim to improve global routing result, but true routability lies in detailed routing. Predicting detailed routing routability in placement is extremely difficult due to the complexity and uncertainty of routing. In this paper, we propose a new detailed routing routability prediction model based on supervised learning. After extracting key features in placement and detailed routing, multivariate adaptive regression is performed to train the connection between these two stages. Using a well-trained model, most design rule violations after detailed routing can be foreseen in placement stage. Experiments show that our average prediction accuracy is 79.8%, which is comparable with other state-of-art routability estimation techniques.

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“…As a result, the constraints and the objectives of higher layers, such as the system or logic level, are very difficult to be mapped into those of lower layers, such as physical design, and viceversa, thereby creating a gap between the optimality at the logic stage and the physical design stage. This necessitates the innovation of data-driven methodologies, such as machine learning [1]- [5], to bridge this gap.…”

Section: Introductionmentioning

confidence: 99%

Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach

Roy

Jin

et al. 2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become sub-optimal after going through physical design flow. Adder design has been such a long studied fundamental problem in VLSI industry yet designers cannot achieve optimal solutions by running EDA tools on the set of available prefix adder architectures. In this paper, we enhance a state-of-theart prefix adder synthesis algorithm to obtain a much wider solution space in architectural domain. On top of that, a machine learning-based design space exploration methodology is applied to predict the Pareto frontier of the adders in physical domain, which is infeasible by exhaustively running EDA tools for innumerable architectural solutions. Considering the high cost of obtaining the true values for learning, an active learning algorithm is proposed to select the representative data during learning process, which uses less labeled data while achieving better quality of Pareto frontier. Experimental results demonstrate that our framework can achieve Pareto frontier of high quality over a wide design space, bridging the gap between architectural and physical designs. Source code and data are available at https

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Machine learning and pattern matching in physical design

Cited by 36 publications

References 45 publications

Effective datapath logic extraction techniques using connection vectors

Effective datapath logic extraction techniques using connection vectors

An accurate detailed routing routability prediction model in placement

Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach

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