Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach

Abstract

In spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become sub-optimal after going through physical design flow. Adder design has been such a long studied fundamental problem in VLSI industry yet designers cannot achieve optimal solutions by running EDA tools on the set of available prefix adder architectures. In this paper, we enhance a state-of-theart prefix adder synthesis algorithm to obtain a much wider solution space in architectural domain. On top of that, a machine learning-based design space exploration methodology is applied to predict the Pareto frontier of the adders in physical domain, which is infeasible by exhaustively running EDA tools for innumerable architectural solutions. Considering the high cost of obtaining the true values for learning, an active learning algorithm is proposed to select the representative data during learning process, which uses less labeled data while achieving better quality of Pareto frontier. Experimental results demonstrate that our framework can achieve Pareto frontier of high quality over a wide design space, bridging the gap between architectural and physical designs. Source code and data are available at https

Machine Learning for Electronic Design Automation: A Survey

“…The key techniques are to find an underlying surrogate model, and a search strategy to sample new design points. Options of the surrogate model include GP, along with all the models used in performance prediction [102,109]. Search strategies are usually heuristics from domain knowledge, including uniformly random exploration [93], exploring the most uncertain designs [177], exploring and eliminating the worst designs [109], etc.…”

Development of Multiobjective High-Level Synthesis for FPGAs

“…e exploration methodology is divided into five steps: initial sampling, clustering, cluster selection, intracluster exploration, and intercluster exploration. Ma et al [81] presented a Gaussian process regression to optimize simultaneously delay, area, and power. Machine learning is applied to predict the PF approximation of the adders in the physical domain, because it is infeasible to exhaustively run the HLS tools for many architectural solutions.…”

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow

“…In [6], an automated selection mechanism based on searching the design space in parallel while pruning non-competitive solutions at early stage is exploited, rather than propagating through the entire design flow. In [4], machine learning approaches were employed to bridge the synthesis solution space to the physical solution space, with the goal to enable Pareto-driven exploration for high speed and power efficient adder designs.…”