NEST: a nonenumerative test generation method for path delay faults in combinational circuits

Pomeranz, Irith; Reddy, S.M.; Uppaluri, P.

doi:10.1109/43.476581

Cited by 44 publications

(18 citation statements)

References 21 publications

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“…The problem of handling large numbers of paths was alleviated in part by the non-enumerative methods of [3,6], however, even using these techniques, the fault coverage for large circuits is still very low. This is due in part to the large number of tests to detect all faults, and in part to the fact that many of the faults are untestable.…”

Section: Introductionmentioning

confidence: 99%

“…At the same time, it also increases the testability of the original paths, by allowing the test generation objectives for different subpaths of the same original path to be satisfied separately, by different tests. Without the observation that test-points divide the circuit paths for testing purposes, even large numbers of test-points do not achieve high fault coverage in [6].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design-for-testability for path delay faults in large combinational circuits using test points

Pomeranz

Reddy

1998

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability. Using an appropriate test application scheme with multiple clock periods, a test-point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g, and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested directly is thus reduced. Test-point insertion is done to reduce the number of paths, using a time-efficient procedure. Indirectly, it also reduces the number of tests and renders untestable paths testable. Experimental results are presented to demonstrate the effectiveness of the method proposed in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design-for-testability for path delay faults in large combinational circuits using test points

Pomeranz

Reddy

1998

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…[14][15][16], do not target any specific path, but generate tests for all PDFs in the circuit. By this, enumerating a potentially exponential number of paths in a circuit is avoided.…”

Section: Related Workmentioning

confidence: 99%

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics

Eggersglüβ

Fey

Glowatz³

et al. 2010

J Electron Test

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As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to detect small delay defects and to verify the correct temporal behavior of a circuit.In this article, MONSOON, an efficient SAT-based approach for generating non-robust and robust test patterns for path delay faults is presented. MONSOON handles tri-state elements and environmental constraints occurring in industrial practice using multiple-valued logics. Structural techniques increase the efficiency of the algorithm. A comparison with a state-of-the-art approach shows a significant speed-up. Experimental results for large industrial circuits demonstrates the feasibility and robustness of MONSOON.

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“…However, since the number of modeled path faults and the machines used are different, a direct comparison may not be meaningful. It may be noticed that the fraction of modeled paths that are robustly tested in our method is significantly higher than that reported in [14,151. The results support the merit of selecting the longest and shortest paths and the efficiency of the novel ideas in our system.…”

Section: (S)mentioning

confidence: 58%

“…There are several methods available in the literature for the selection of a subset of paths [13]. Recently, Pomeranz e t a1 [14] and Heragu [9] have described methods without enumerating paths. In recent papers [8,111, it has been shown that the determination of an optimal clocking period highly depends on the accuracies of the estimated longest path length and the shortest path length in the circuit.…”

Section: Test Generationmentioning

confidence: 99%

An efficient automatic test generation system for path delay faults in combinational circuits

Majhi

Jacob

Patnaik³

et al.

Proceedings of the 8th International Conference on VLSI Design

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NEST: a nonenumerative test generation method for path delay faults in combinational circuits

Cited by 44 publications

References 21 publications

Design-for-testability for path delay faults in large combinational circuits using test points

Design-for-testability for path delay faults in large combinational circuits using test points

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics

An efficient automatic test generation system for path delay faults in combinational circuits

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