1998
DOI: 10.1109/43.703823
|View full text |Cite
|
Sign up to set email alerts
|

Design-for-testability for path delay faults in large combinational circuits using test points

Abstract: We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability. Using an appropriate test application scheme with multiple clock periods, a test-point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g, and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested directly is thus reduced. Test… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
4
1

Citation Types

0
36
0

Year Published

1998
1998
2013
2013

Publication Types

Select...
3
2
1

Relationship

0
6

Authors

Journals

citations
Cited by 34 publications
(36 citation statements)
references
References 34 publications
0
36
0
Order By: Relevance
“…Pomeranz and Kohavi [10] proposed an optimization method for test-point insertion for general combinational circuits. More recently, Pomeranz and Reddy [11] proposed 0278-0070/97$10.00 © 1997 IEEE a technique to insert test points to improve significantly the path delay fault coverage of large combinational circuits. A technique to provide test points is "bed of nails" [12], where the tester probes the underside of a board so that numerous, spatially isodistant points of controllability and observability are provided.…”
Section: A Nonscan Dft Using Test Pointsmentioning
confidence: 99%
“…Pomeranz and Kohavi [10] proposed an optimization method for test-point insertion for general combinational circuits. More recently, Pomeranz and Reddy [11] proposed 0278-0070/97$10.00 © 1997 IEEE a technique to insert test points to improve significantly the path delay fault coverage of large combinational circuits. A technique to provide test points is "bed of nails" [12], where the tester probes the underside of a board so that numerous, spatially isodistant points of controllability and observability are provided.…”
Section: A Nonscan Dft Using Test Pointsmentioning
confidence: 99%
“…The main TPI disadvantages are the additional silicon area required, but most of all, the impact on the circuit's timing, leading to timing violations, which may require several design iterations [33]. These violations occur because the presence of a (complete) test point (aimed at improving both observability and controllability) adds gates on the target path: two additional gates are required in [25,31], with 2 muxes in the case of transparent scan flip-flops [33].…”
Section: Test Point Insertionmentioning
confidence: 97%
“…However, with delay faults, it becomes more complex to deal with the related synchronization aspect. Some have proposed the use of special additional clocks [22,25], which require additional routing resources and may lead to more routing congestion problems as these resources are limited [23]. When the regular clock is used, it impacts the "size" of delay defects that can be detected.…”
Section: Test Point Insertionmentioning
confidence: 98%
See 1 more Smart Citation
“…This means that 1.2V becomes the essential test Vdd and TPI has to include it for 100% defect coverage, as the resistance range covered at 1.2V cannot be covered at 0.8V. Other than that TPI has some wellaccepted limitations (not limited to the scheme proposed in [9]) that to increase the fault coverage and to reduce test cost it may be necessary to introduce extra overhead on timing, area and power as is the case with [10]- [12]. For instance, a test point (control point) added to the critical path may violate the timing, which restricts its usage in critical paths.…”
Section: Preliminariesmentioning
confidence: 99%