Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing

Abstract

Abstract-Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% defect coverage; however switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective Gate Sizing technique for reducing test cost of multi-Vdd designs with bridge defects. Using synthesized ISCAS benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves 100% defect coverage at a single Vdd setting; in addition it has a lower overhead than the recently proposed Test Point Insertion technique in terms of timing, area and power.

Test Strategies for Multivoltage Designs

“…One drawback with TPI scheme [Khursheed et al 2008] is that it does not guarantee single Vdd test and usually results in more than one test Vdd settings. Experimental results presented in [Khursheed et al 2008] and more recently in [Khursheed et al 2009a] show that TPI is unable to reduce test to single Vdd setting for majority of circuits. This can be understood from the following explanation.…”

“…On the other hand, a physical defect between an interconnect line and power supply (Vdd) or ground rail (Gnd) is referred to as hard-short (bridge with 0 Ω resistance). It was shown in [Khursheed et al 2009b] that detectability of hard-short is irrespective of Vdd settings and therefore is not further discussed in this chapter. This section discusses modelling and test generation of resistive bridge for multi-Vdd designs.…”

“…Recently a new technique for reducing test cost of multi-Vdd designs with resistive bridging defect has been reported in [Khursheed et al 2009a]. It targets resistive bridge that cause faulty logic behavior to appear at a non-desired test Vdd setting and uses Gate Sizing (GS) to expose the same physical resistance at preferred test Vdd.…”

“…In Fig. 8 Experiments are conducted using ISCAS'85 and '89 full scan circuits, and results for TPI [Khursheed et al 2008] and Gate Sizing [Khursheed et al 2009a] are tabulated in Table 8.2. The first two columns show the benchmark designs and respective gate count in each design.…”

“…The number of gates replaced by GS technique ranges from 1-14, while TPI has added up to 28 test points. In another experiment reported in [Khursheed et al 2009a], the timing performance of the original design (Orig), is compared with the design altered by Gate Sizing (GS) and by Test Point Insertion (TPI) techniques using Synopsys design compiler. Fig.…”