An efficient automatic test generation system for path delay faults in combinational circuits

Majhi, A.K.; Jacob, J.; Patnaik, L. M.; Agrawal, Vishwani D.

doi:10.1109/icvd.1995.512097

Cited by 13 publications

(5 citation statements)

References 18 publications

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“…The test generator [6], [9] is used to derive robust tests for these targeted path faults. Once a test is found, fault simulation is carried out to obtain information on the robust detection of other path faults.…”

Section: Two-pass Test Generationmentioning

confidence: 99%

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Line coverage of path delay faults

Majhi

Agrawak²,

Jacob

et al. 2000

IEEE Trans. VLSI Syst.

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We propose a new coverage metric for delay fault tests. The coverage is measured for each line with a rising and a falling transition, but the test criterion differs from that of the slow-to-rise and slow-to-fall transition faults. A line is tested by a line delay test, which is a robust path delay test for the longest sensitizable path producing a given transition on the target line. Thus, the test criterion resembles path delay test and not the gate or transition delay test. Yet, the maximum number of tests (or faults) is limited to twice the number of lines. In a two-pass test-generation procedure, we first attempt delay tests for a minimal set of longest paths for all lines. Fault simulation is used to determine the coverage metric. For uncovered lines, in the second pass, several paths of decreasing lengths are targeted. We give results for several benchmark circuits.

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Section: Two-pass Test Generationmentioning

confidence: 99%

“…Pipelined cellular arrays [1]- [5] represent an appropriate implementation approach for arithmetic circuits where a high computational speed is required [6]- [9]. They are designed in the form of regularly repeated patterns of identical circuits.…”

Section: Introductionmentioning

confidence: 99%

Line coverage of path delay faults

Majhi

Agrawak²,

Jacob

et al. 2000

IEEE Trans. VLSI Syst.

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“…A pair of test vectors must be applied to test for a path delay fault [3]. Many efficient algorithms have been reported in the literature for generation of delay tests [3][4][5]. However, generating delay tests for a circuit of VLSI complexity can be quite time consuming due to several reasons (a) The number of paths, and hence the number of path delay faults, can be excessively large (b) The test generation for a single delay fault can be time consuming since most test generators used PODEM-like [6] backtracking algorithms and (c) When the circuit description is available at block-level (or macro-level), an overhead is encountered in the flattening of the netlist to gate-level.…”

Section: Introductionmentioning

confidence: 99%

“…Efficient path selection algorithms [7,8] can be used to reduce the size of the fault set. Improved delay test generators (such as the FAN-based algorithm described in [4] or the algorithm based on binary decision diagrams described in [9]) can reduce the test generation time by reducing the number of backtracks or through the use of algebraic techniques). To alleviate the problem of flattening the hierarchical netlist, we propose in this paper a scheme to perform delay test generation at the module level itself.…”

Section: Introductionmentioning

confidence: 99%

Untitled

Ravikumar

Agrawal²,

Agarwal

1997

Journal of Electronic Testing

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Delay testing is used to detect timing errors in a digital circuit. In this paper, we report a tool called MODET for automatic test generation for path delay faults in modular combinational circuits. Our technique uses precomputed robust delay tests for individual modules to compute robust delay tests for the module-level circuit. We present a longest path theorem at the module level of abstraction which specifies the requirements for path selection during delay testing. Based on this theorem, we propose a path selection procedure in module-level circuits and report efficient algorithms for delay test generation. MODET has been tested against a number of hierarchical circuits with impressive speedups in relation to gate-level test generation.

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“…The first pass of our two-pass test generation strat- egy is essentially the same as reported in [7]. Initially a simple path selection method is employed to obtain a list of paths that cover all signal lines by their respective longest structural paths.…”

Section: Two-pass Test Generationmentioning

confidence: 88%

On test coverage of path delay faults

Majhi

Jacob

Patnaik

et al.

Proceedings of 9th International Conference on VLSI Design

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W e propose a coverage metric and a two-pass test generation method f o r path delay faults in combinational logic circuits. The coverage is measured f o r each line with a rising and a falling transition. However, the test criterion is different from that of the slow-to-rise and slow-to-fallIn this paper, we define a rising line delay test that sensitizes the longest sensitizable path passing through the target line producing a rising transition on it. Similarly, a falling line delay test is defined. The definition of "longest" can be appropriately chosen. For example, in the simplest case, it can be the path with largest number of gates. Alternatively, gates can be weighted by their nominal delays. However, once the path is selected, the test generation is independent of gate delays. The criterion of delay test through the longest path has been used for diagnosis [5].The coverage is measured for all lines with two possible transitions. Thus, the maximum number of faults (or tests) is twice the number of lines. Yet, test criterion is similar to path delay fault, and not like gate or transition delay fault. In general, a test will cover several lines. This coverage methodology can also be applied to the reported methods that extract sensitizable paths [2, 31.An iterative approach for generating a robust test was first proposed by Park and Mercer [SI. They devised an approzzmate method where the search space of test generation process is biased to find a test along a path whose propagation delay is greater than or equal to a predefined threshold value. Our approach is to use an exact method for generating a test for the longest robustly testable path through each line. Two-Pass Test GenerationFinding the longest sensitizable and robustly testable path through a given delay fault site is an NP-hard problem [8]. We first attempt to find a robust test for the longest structural path through a line. If the path is not sensitizable, then we try to find a robust test for the next longest structural path, and so forth, until a test for the longest sensitizable path is found. Given enough resources this method guarantees a test for the longest sensitizable path through the line if such a test exists.The first pass of our two-pass test generation strat-

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An efficient automatic test generation system for path delay faults in combinational circuits

Abstract: A bsit ract

Cited by 13 publications

References 18 publications

Line coverage of path delay faults

Line coverage of path delay faults

Untitled

On test coverage of path delay faults

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